Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0+ |
Rick Chen | 64d4ead | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 2 | # |
| 3 | # Copyright (C) 2017 Andes Technology Corporation. |
| 4 | # Rick Chen, Andes Technology Corporation <rick@andestech.com> |
Rick Chen | 64d4ead | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 5 | |
Lukas Auer | 17d3e90 | 2018-11-22 11:26:15 +0100 | [diff] [blame] | 6 | ifeq ($(CONFIG_ARCH_RV64I),y) |
| 7 | ARCH_BASE = rv64im |
Heinrich Schuchardt | c66c950 | 2022-10-12 14:59:51 +0200 | [diff] [blame] | 8 | ABI_BASE = lp64 |
Lukas Auer | 17d3e90 | 2018-11-22 11:26:15 +0100 | [diff] [blame] | 9 | endif |
| 10 | ifeq ($(CONFIG_ARCH_RV32I),y) |
| 11 | ARCH_BASE = rv32im |
Heinrich Schuchardt | c66c950 | 2022-10-12 14:59:51 +0200 | [diff] [blame] | 12 | ABI_BASE = ilp32 |
Lukas Auer | 17d3e90 | 2018-11-22 11:26:15 +0100 | [diff] [blame] | 13 | endif |
| 14 | ifeq ($(CONFIG_RISCV_ISA_A),y) |
| 15 | ARCH_A = a |
| 16 | endif |
Heinrich Schuchardt | c66c950 | 2022-10-12 14:59:51 +0200 | [diff] [blame] | 17 | ifeq ($(CONFIG_RISCV_ISA_F),y) |
| 18 | ARCH_F = f |
| 19 | endif |
| 20 | ifeq ($(CONFIG_RISCV_ISA_D),y) |
| 21 | ARCH_D = d |
| 22 | ABI_D = d |
| 23 | endif |
Lukas Auer | 17d3e90 | 2018-11-22 11:26:15 +0100 | [diff] [blame] | 24 | ifeq ($(CONFIG_RISCV_ISA_C),y) |
| 25 | ARCH_C = c |
| 26 | endif |
Lukas Auer | ecc5d83 | 2018-12-12 06:12:23 -0800 | [diff] [blame] | 27 | ifeq ($(CONFIG_CMODEL_MEDLOW),y) |
| 28 | CMODEL = medlow |
| 29 | endif |
| 30 | ifeq ($(CONFIG_CMODEL_MEDANY),y) |
| 31 | CMODEL = medany |
| 32 | endif |
Lukas Auer | 17d3e90 | 2018-11-22 11:26:15 +0100 | [diff] [blame] | 33 | |
Heinrich Schuchardt | c66c950 | 2022-10-12 14:59:51 +0200 | [diff] [blame] | 34 | |
| 35 | RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) |
| 36 | ABI = $(ABI_BASE)$(ABI_D) |
Alexandre Ghiti | 43e1f93 | 2022-10-03 18:07:54 +0200 | [diff] [blame] | 37 | |
| 38 | # Newer binutils versions default to ISA spec version 20191213 which moves some |
| 39 | # instructions from the I extension to the Zicsr and Zifencei extensions. |
| 40 | toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) |
| 41 | ifeq ($(toolchain-need-zicsr-zifencei),y) |
| 42 | RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei |
| 43 | endif |
| 44 | |
| 45 | ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ |
Lukas Auer | ecc5d83 | 2018-12-12 06:12:23 -0800 | [diff] [blame] | 46 | -mcmodel=$(CMODEL) |
Lukas Auer | 17d3e90 | 2018-11-22 11:26:15 +0100 | [diff] [blame] | 47 | |
| 48 | PLATFORM_CPPFLAGS += $(ARCH_FLAGS) |
| 49 | CFLAGS_EFI += $(ARCH_FLAGS) |
| 50 | |
Bin Meng | bcb3843 | 2018-09-26 06:55:17 -0700 | [diff] [blame] | 51 | head-y := arch/riscv/cpu/start.o |
Rick Chen | 64d4ead | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 52 | |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 53 | libs-y += arch/riscv/cpu/ |
Rick Chen | 64d4ead | 2017-12-26 13:55:52 +0800 | [diff] [blame] | 54 | libs-y += arch/riscv/cpu/$(CPU)/ |
| 55 | libs-y += arch/riscv/lib/ |