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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +05302/*
3 * Freescale Layerscape MC I/O wrapper
4 *
Yogesh Gaur1a0c4ae2018-05-09 10:52:17 +05305 * Copyright 2015-2016 Freescale Semiconductor, Inc.
Yogesh Gaur318c32f2017-11-15 11:59:31 +05306 * Copyright 2017 NXP
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +05307 * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +05308 */
9
10#ifndef __FSL_DPMAC_H
11#define __FSL_DPMAC_H
12
13/* DPMAC Version */
Yogesh Gaur318c32f2017-11-15 11:59:31 +053014#define DPMAC_VER_MAJOR 4
Prabhakar Kushwahac3d06e32015-12-24 15:32:49 +053015#define DPMAC_VER_MINOR 2
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053016
17/* Command IDs */
Yogesh Gaur318c32f2017-11-15 11:59:31 +053018#define DPMAC_CMDID_CLOSE 0x8001
19#define DPMAC_CMDID_OPEN 0x80c1
20#define DPMAC_CMDID_CREATE 0x90c1
21#define DPMAC_CMDID_DESTROY 0x98c1
22#define DPMAC_CMDID_GET_API_VERSION 0xa0c1
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053023
Yogesh Gaur318c32f2017-11-15 11:59:31 +053024#define DPMAC_CMDID_RESET 0x0051
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053025
Yogesh Gaur318c32f2017-11-15 11:59:31 +053026#define DPMAC_CMDID_SET_LINK_STATE 0x0c31
27#define DPMAC_CMDID_GET_COUNTER 0x0c41
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053028
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +030029/* Macros for accessing command fields smaller than 1byte */
30#define DPMAC_MASK(field) \
31 GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \
32 DPMAC_##field##_SHIFT)
33#define dpmac_set_field(var, field, val) \
34 ((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field)))
35#define dpmac_get_field(var, field) \
36 (((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT)
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053037
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +030038#pragma pack(push, 1)
39struct dpmac_cmd_open {
40 __le32 dpmac_id;
41};
42
43struct dpmac_cmd_create {
44 __le32 mac_id;
45};
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053046
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +030047struct dpmac_cmd_destroy {
48 __le32 dpmac_id;
49};
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053050
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +030051#define DPMAC_STATE_SIZE 1
52#define DPMAC_STATE_SHIFT 0
53#define DPMAC_STATE_VALID_SIZE 1
54#define DPMAC_STATE_VALID_SHIFT 1
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053055
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +030056struct dpmac_cmd_set_link_state {
57 __le64 options;
58 __le32 rate;
59 __le32 pad;
60 /* only least significant bit is valid */
61 u8 up;
62 u8 pad0[7];
63 __le64 supported;
64 __le64 advertising;
65};
66
67struct dpmac_cmd_get_counter {
68 u8 type;
69};
70
71struct dpmac_rsp_get_counter {
72 __le64 pad;
73 __le64 counter;
74};
75
76#pragma pack(pop)
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053077
78/* Data Path MAC API
79 * Contains initialization APIs and runtime control APIs for DPMAC
80 */
81
82struct fsl_mc_io;
83
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +030084int dpmac_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpmac_id, u16 *token);
85
86int dpmac_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053087
88/**
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +030089 * struct dpmac_cfg - Structure representing DPMAC configuration
90 * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP,
91 * the MAC IDs are continuous.
92 * For example: 2 WRIOPs, 16 MACs in each:
93 * MAC IDs for the 1st WRIOP: 1-16,
94 * MAC IDs for the 2nd WRIOP: 17-32.
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +053095 */
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +030096struct dpmac_cfg {
97 int mac_id;
98};
99
100int dpmac_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
101 const struct dpmac_cfg *cfg, u32 *obj_id);
102
103int dpmac_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
104 u32 object_id);
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530105
106/**
107 * enum dpmac_link_type - DPMAC link type
108 * @DPMAC_LINK_TYPE_NONE: No link
109 * @DPMAC_LINK_TYPE_FIXED: Link is fixed type
110 * @DPMAC_LINK_TYPE_PHY: Link by PHY ID
111 * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
112 */
113enum dpmac_link_type {
114 DPMAC_LINK_TYPE_NONE,
115 DPMAC_LINK_TYPE_FIXED,
116 DPMAC_LINK_TYPE_PHY,
117 DPMAC_LINK_TYPE_BACKPLANE
118};
119
120/**
121 * enum dpmac_eth_if - DPMAC Ethrnet interface
122 * @DPMAC_ETH_IF_MII: MII interface
123 * @DPMAC_ETH_IF_RMII: RMII interface
124 * @DPMAC_ETH_IF_SMII: SMII interface
125 * @DPMAC_ETH_IF_GMII: GMII interface
126 * @DPMAC_ETH_IF_RGMII: RGMII interface
127 * @DPMAC_ETH_IF_SGMII: SGMII interface
128 * @DPMAC_ETH_IF_QSGMII: QSGMII interface
129 * @DPMAC_ETH_IF_XAUI: XAUI interface
130 * @DPMAC_ETH_IF_XFI: XFI interface
131 */
132enum dpmac_eth_if {
133 DPMAC_ETH_IF_MII,
134 DPMAC_ETH_IF_RMII,
135 DPMAC_ETH_IF_SMII,
136 DPMAC_ETH_IF_GMII,
137 DPMAC_ETH_IF_RGMII,
138 DPMAC_ETH_IF_SGMII,
139 DPMAC_ETH_IF_QSGMII,
140 DPMAC_ETH_IF_XAUI,
141 DPMAC_ETH_IF_XFI
142};
143
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530144/* DPMAC IRQ Index and Events */
145
146/* IRQ index */
147#define DPMAC_IRQ_INDEX 0
148/* IRQ event - indicates a change in link state */
149#define DPMAC_IRQ_EVENT_LINK_CFG_REQ 0x00000001
150/* irq event - Indicates that the link state changed */
151#define DPMAC_IRQ_EVENT_LINK_CHANGED 0x00000002
152
153/**
154 * struct dpmac_attr - Structure representing DPMAC attributes
155 * @id: DPMAC object ID
156 * @phy_id: PHY ID
157 * @link_type: link type
158 * @eth_if: Ethernet interface
159 * @max_rate: Maximum supported rate - in Mbps
160 * @version: DPMAC version
161 */
162struct dpmac_attr {
163 int id;
164 int phy_id;
165 enum dpmac_link_type link_type;
166 enum dpmac_eth_if eth_if;
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +0300167 u32 max_rate;
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530168};
169
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530170/* DPMAC link configuration/state options */
171
172/* Enable auto-negotiation */
173#define DPMAC_LINK_OPT_AUTONEG 0x0000000000000001ULL
174/* Enable half-duplex mode */
175#define DPMAC_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL
176/* Enable pause frames */
177#define DPMAC_LINK_OPT_PAUSE 0x0000000000000004ULL
178/* Enable a-symmetric pause frames */
179#define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL
180
181/**
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530182 * struct dpmac_link_state - DPMAC link configuration request
183 * @rate: Rate in Mbps
184 * @options: Enable/Disable DPMAC link cfg features (bitmap)
185 * @up: Link state
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +0300186 * @state_valid: Ignore/Update the state of the link
187 * @supported: Speeds capability of the phy (bitmap)
188 * @advertising: Speeds that are advertised for autoneg (bitmap)
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530189 */
190struct dpmac_link_state {
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +0300191 u32 rate;
192 u64 options;
193 int up;
194 int state_valid;
195 u64 supported;
196 u64 advertising;
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530197};
198
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +0300199int dpmac_set_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
200 struct dpmac_link_state *link_state);
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530201/**
202 * enum dpni_counter - DPNI counter types
203 * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad.
204 * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-octet frame, good or bad.
205 * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-octet frame, good or bad.
206 * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-octet frame, good or bad.
207 * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-octet frame, good or bad.
208 * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-octet frame, good or bad.
209 * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-octet frame and larger
210 * (up to max frame length specified),
211 * good or bad.
212 * @DPMAC_CNT_ING_FRAG: counts packet which is shorter than 64 octets received
213 * with a wrong CRC
214 * @DPMAC_CNT_ING_JABBER: counts packet longer than the maximum frame length
215 * specified, with a bad frame check sequence.
216 * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped packet due to internal errors.
217 * Occurs when a receive FIFO overflows.
218 * Includes also packets truncated as a result of
219 * the receive FIFO overflow.
220 * @DPMAC_CNT_ING_ALIGN_ERR: counts frame with an alignment error
221 * (optional used for wrong SFD)
222 * @DPMAC_CNT_EGR_UNDERSIZED: counts packet transmitted that was less than 64
223 * octets long with a good CRC.
224 * @DPMAC_CNT_ING_OVERSIZED: counts packet longer than the maximum frame length
225 * specified, with a good frame check sequence.
226 * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frame (regular and PFC).
227 * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frame transmitted
228 * (regular and PFC).
229 * @DPMAC_CNT_ING_BYTE: counts octet received except preamble for all valid
230 * frames and valid pause frames.
231 * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frame
232 * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frame
233 * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad packet received.
234 * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frame
235 * @DPMAC_CNT_ING_ERR_FRAME: counts frame received with an error
236 * (except for undersized/fragment frame)
237 * @DPMAC_CNT_EGR_BYTE: counts octet transmitted except preamble for all valid
238 * frames and valid pause frames transmitted.
239 * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frame
240 * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frame
241 * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frame
242 * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error
243 * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including
244 * pause frames.
Ioana Ciornei98fdaaa2023-05-23 16:47:46 +0300245 * @DPMAC_CNT_EGR_GOOD_FRAME: counts frames transmitted without error, including
246 * pause frames.
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530247 */
248enum dpmac_counter {
249 DPMAC_CNT_ING_FRAME_64,
250 DPMAC_CNT_ING_FRAME_127,
251 DPMAC_CNT_ING_FRAME_255,
252 DPMAC_CNT_ING_FRAME_511,
253 DPMAC_CNT_ING_FRAME_1023,
254 DPMAC_CNT_ING_FRAME_1518,
255 DPMAC_CNT_ING_FRAME_1519_MAX,
256 DPMAC_CNT_ING_FRAG,
257 DPMAC_CNT_ING_JABBER,
258 DPMAC_CNT_ING_FRAME_DISCARD,
259 DPMAC_CNT_ING_ALIGN_ERR,
260 DPMAC_CNT_EGR_UNDERSIZED,
261 DPMAC_CNT_ING_OVERSIZED,
262 DPMAC_CNT_ING_VALID_PAUSE_FRAME,
263 DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
264 DPMAC_CNT_ING_BYTE,
265 DPMAC_CNT_ING_MCAST_FRAME,
266 DPMAC_CNT_ING_BCAST_FRAME,
267 DPMAC_CNT_ING_ALL_FRAME,
268 DPMAC_CNT_ING_UCAST_FRAME,
269 DPMAC_CNT_ING_ERR_FRAME,
270 DPMAC_CNT_EGR_BYTE,
271 DPMAC_CNT_EGR_MCAST_FRAME,
272 DPMAC_CNT_EGR_BCAST_FRAME,
273 DPMAC_CNT_EGR_UCAST_FRAME,
274 DPMAC_CNT_EGR_ERR_FRAME,
Ioana Ciornei98fdaaa2023-05-23 16:47:46 +0300275 DPMAC_CNT_ING_GOOD_FRAME,
276 DPMAC_CNT_EGR_GOOD_FRAME,
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530277};
278
Ioana Ciornei0ef7e5a2023-05-31 19:04:31 +0300279int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
280 enum dpmac_counter type, u64 *counter);
281
282int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
283 u16 *major_ver, u16 *minor_ver);
Prabhakar Kushwaha916ef9f2015-11-04 12:25:54 +0530284
285#endif /* __FSL_DPMAC_H */