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git01.mediatek.com / filogic / uboot / 7d6bbb9c5568d892ae798f362a354d0dc09d8a19 / . / drivers / net / npe / include / IxOsalOsIxp400.h
blob: 104c733e3b84f9e47d2385407c464ba9f5d2d6c8 [file] [log] [blame]
Wolfgang Denk4646d2a2006-05-30 15:56:48 +0200[diff] [blame]1/**
2 * @file IxOsalOsIxp400.h
3 *
4 * @brief OS and platform specific definitions
5 *
6 * Design Notes:
7 *
8 * @par
9 * IXP400 SW Release version 2.0
10 *
11 * -- Copyright Notice --
12 *
13 * @par
14 * Copyright 2001-2005, Intel Corporation.
15 * All rights reserved.
16 *
17 * @par
Wolfgang Denkc57eadc2013-07-28 22:12:47 +0200[diff] [blame]18 * SPDX-License-Identifier: BSD-3-Clause
Wolfgang Denk4646d2a2006-05-30 15:56:48 +0200[diff] [blame]19 * @par
20 * -- End of Copyright Notice --
21 */
22
23#ifndef IxOsalOsIxp400_H
24#define IxOsalOsIxp400_H
25
26#define BIT(x) (1<<(x))
27
28#define IXP425_EthA_BASE 0xc8009000
29#define IXP425_EthB_BASE 0xc800a000
30
31#define IXP425_PSMA_BASE 0xc8006000
32#define IXP425_PSMB_BASE 0xc8007000
33#define IXP425_PSMC_BASE 0xc8008000
34
35#define IXP425_PERIPHERAL_BASE 0xc8000000
36
37#define IXP425_QMGR_BASE 0x60000000
38#define IXP425_OSTS 0xC8005000
39
40#define IXP425_INT_LVL_NPEA 0
41#define IXP425_INT_LVL_NPEB 1
42#define IXP425_INT_LVL_NPEC 2
43
44#define IXP425_INT_LVL_QM1 3
45#define IXP425_INT_LVL_QM2 4
46
47#define IXP425_EXPANSION_BUS_BASE1 0x50000000
48#define IXP425_EXPANSION_BUS_BASE2 0x50000000
49#define IXP425_EXPANSION_BUS_CS1_BASE 0x51000000
50
51#define IXP425_EXP_CONFIG_BASE 0xC4000000
52
53/* physical addresses to be used when requesting memory with IX_OSAL_MEM_MAP */
54#define IX_OSAL_IXP400_INTC_PHYS_BASE IXP425_INTC_BASE
55#define IX_OSAL_IXP400_GPIO_PHYS_BASE IXP425_GPIO_BASE
56#define IX_OSAL_IXP400_UART1_PHYS_BASE IXP425_UART1_BASE
57#define IX_OSAL_IXP400_UART2_PHYS_BASE IXP425_UART2_BASE
58#define IX_OSAL_IXP400_ETHA_PHYS_BASE IXP425_EthA_BASE
59#define IX_OSAL_IXP400_ETHB_PHYS_BASE IXP425_EthB_BASE
60#define IX_OSAL_IXP400_NPEA_PHYS_BASE IXP425_NPEA_BASE
61#define IX_OSAL_IXP400_NPEB_PHYS_BASE IXP425_NPEB_BASE
62#define IX_OSAL_IXP400_NPEC_PHYS_BASE IXP425_NPEC_BASE
63#define IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE IXP425_PERIPHERAL_BASE
64#define IX_OSAL_IXP400_QMGR_PHYS_BASE IXP425_QMGR_BASE
65#define IX_OSAL_IXP400_OSTS_PHYS_BASE IXP425_TIMER_BASE
66#define IX_OSAL_IXP400_USB_PHYS_BASE IXP425_USB_BASE
67#define IX_OSAL_IXP400_EXP_CFG_PHYS_BASE IXP425_EXP_CFG_BASE
68#define IX_OSAL_IXP400_EXP_BUS_PHYS_BASE IXP425_EXP_BUS_BASE2
69#define IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE IXP425_EXP_BUS_BASE1
70#define IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE IXP425_EXP_BUS_CS0_BASE
71#define IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE IXP425_EXP_BUS_CS1_BASE
72#define IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE IXP425_EXP_BUS_CS4_BASE
73#define IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE IXP425_EXP_CFG_BASE
74#define IX_OSAL_IXP400_PCI_CFG_PHYS_BASE IXP425_PCI_CFG_BASE
75
76/* map sizes to be used when requesting memory with IX_OSAL_MEM_MAP */
77#define IX_OSAL_IXP400_QMGR_MAP_SIZE (0x4000) /**< Queue Manager map size */
78#define IX_OSAL_IXP400_PERIPHERAL_MAP_SIZE (0xC000) /**< Peripheral space map size */
79#define IX_OSAL_IXP400_UART1_MAP_SIZE (0x1000) /**< UART1 map size */
80#define IX_OSAL_IXP400_UART2_MAP_SIZE (0x1000) /**< UART2 map size */
81#define IX_OSAL_IXP400_PMU_MAP_SIZE (0x1000) /**< PMU map size */
82#define IX_OSAL_IXP400_OSTS_MAP_SIZE (0x1000) /**< OS Timers map size */
83#define IX_OSAL_IXP400_NPEA_MAP_SIZE (0x1000) /**< NPE A map size */
84#define IX_OSAL_IXP400_NPEB_MAP_SIZE (0x1000) /**< NPE B map size */
85#define IX_OSAL_IXP400_NPEC_MAP_SIZE (0x1000) /**< NPE C map size */
86#define IX_OSAL_IXP400_ETHA_MAP_SIZE (0x1000) /**< Eth A map size */
87#define IX_OSAL_IXP400_ETHB_MAP_SIZE (0x1000) /**< Eth B map size */
88#define IX_OSAL_IXP400_USB_MAP_SIZE (0x1000) /**< USB map size */
89#define IX_OSAL_IXP400_GPIO_MAP_SIZE (0x1000) /**< GPIO map size */
90#define IX_OSAL_IXP400_EXP_REG_MAP_SIZE (0x1000) /**< Exp Bus Config Registers map size */
91#define IX_OSAL_IXP400_EXP_BUS_MAP_SIZE (0x08000000) /**< Expansion bus map size */
92#define IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE (0x01000000) /**< CS0 map size */
93#define IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE (0x01000000) /**< CS1 map size */
94#define IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE (0x01000000) /**< CS4 map size */
95#define IX_OSAL_IXP400_PCI_CFG_MAP_SIZE (0x1000) /**< PCI Bus Config Registers map size */
96
97#define IX_OSAL_IXP400_EXP_FUSE (IXP425_EXP_CONFIG_BASE + 0x28)
98#define IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE 0xC800C000
99#define IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE 0x1000
100
101/*
102 * Interrupt Levels
103 */
104#define IX_OSAL_IXP400_NPEA_IRQ_LVL (0)
105#define IX_OSAL_IXP400_NPEB_IRQ_LVL (1)
106#define IX_OSAL_IXP400_NPEC_IRQ_LVL (2)
107#define IX_OSAL_IXP400_QM1_IRQ_LVL (3)
108#define IX_OSAL_IXP400_QM2_IRQ_LVL (4)
109#define IX_OSAL_IXP400_TIMER1_IRQ_LVL (5)
110#define IX_OSAL_IXP400_GPIO0_IRQ_LVL (6)
111#define IX_OSAL_IXP400_GPIO1_IRQ_LVL (7)
112#define IX_OSAL_IXP400_PCI_INT_IRQ_LVL (8)
113#define IX_OSAL_IXP400_PCI_DMA1_IRQ_LVL (9)
114#define IX_OSAL_IXP400_PCI_DMA2_IRQ_LVL (10)
115#define IX_OSAL_IXP400_TIMER2_IRQ_LVL (11)
116#define IX_OSAL_IXP400_USB_IRQ_LVL (12)
117#define IX_OSAL_IXP400_UART2_IRQ_LVL (13)
118#define IX_OSAL_IXP400_TIMESTAMP_IRQ_LVL (14)
119#define IX_OSAL_IXP400_UART1_IRQ_LVL (15)
120#define IX_OSAL_IXP400_WDOG_IRQ_LVL (16)
121#define IX_OSAL_IXP400_AHB_PMU_IRQ_LVL (17)
122#define IX_OSAL_IXP400_XSCALE_PMU_IRQ_LVL (18)
123#define IX_OSAL_IXP400_GPIO2_IRQ_LVL (19)
124#define IX_OSAL_IXP400_GPIO3_IRQ_LVL (20)
125#define IX_OSAL_IXP400_GPIO4_IRQ_LVL (21)
126#define IX_OSAL_IXP400_GPIO5_IRQ_LVL (22)
127#define IX_OSAL_IXP400_GPIO6_IRQ_LVL (23)
128#define IX_OSAL_IXP400_GPIO7_IRQ_LVL (24)
129#define IX_OSAL_IXP400_GPIO8_IRQ_LVL (25)
130#define IX_OSAL_IXP400_GPIO9_IRQ_LVL (26)
131#define IX_OSAL_IXP400_GPIO10_IRQ_LVL (27)
132#define IX_OSAL_IXP400_GPIO11_IRQ_LVL (28)
133#define IX_OSAL_IXP400_GPIO12_IRQ_LVL (29)
134#define IX_OSAL_IXP400_SW_INT1_IRQ_LVL (30)
135#define IX_OSAL_IXP400_SW_INT2_IRQ_LVL (31)
136
137/* USB interrupt level mask */
138#define IX_OSAL_IXP400_INT_LVL_USB IRQ_IXP425_USB
139
140/* USB IRQ */
141#define IX_OSAL_IXP400_USB_IRQ IRQ_IXP425_USB
142
143/*
144 * OS name retrieval
145 */
146#define IX_OSAL_OEM_OS_NAME_GET(name, limit) \
147ixOsalOsIxp400NameGet((INT8*)(name), (INT32) (limit))
148
149/*
150 * OS version retrieval
151 */
152#define IX_OSAL_OEM_OS_VERSION_GET(version, limit) \
153ixOsalOsIxp400VersionGet((INT8*)(version), (INT32) (limit))
154
155/*
156 * Function to retrieve the OS name
157 */
158PUBLIC IX_STATUS ixOsalOsIxp400NameGet(INT8* osName, INT32 maxSize);
159
160/*
161 * Function to retrieve the OS version
162 */
163PUBLIC IX_STATUS ixOsalOsIxp400VersionGet(INT8* osVersion, INT32 maxSize);
164
165/*
166 * TimestampGet
167 */
168PUBLIC UINT32 ixOsalOsIxp400TimestampGet (void);
169
170/*
171 * Timestamp
172 */
173#define IX_OSAL_OEM_TIMESTAMP_GET ixOsalOsIxp400TimestampGet
174
175
176/*
177 * Timestamp resolution
178 */
179PUBLIC UINT32 ixOsalOsIxp400TimestampResolutionGet (void);
180
181#define IX_OSAL_OEM_TIMESTAMP_RESOLUTION_GET ixOsalOsIxp400TimestampResolutionGet
182
183/*
184 * Retrieves the system clock rate
185 */
186PUBLIC UINT32 ixOsalOsIxp400SysClockRateGet (void);
187
188#define IX_OSAL_OEM_SYS_CLOCK_RATE_GET ixOsalOsIxp400SysClockRateGet
189
190/*
191 * required by FS but is not really platform-specific.
192 */
193#define IX_OSAL_OEM_TIME_GET(pTv) ixOsalTimeGet(pTv)
194
195
196
197/* linux map/unmap functions */
198PUBLIC void ixOsalLinuxMemMap (IxOsalMemoryMap * map);
199
200PUBLIC void ixOsalLinuxMemUnmap (IxOsalMemoryMap * map);
201
202
203/*********************
204 * Memory map
205 ********************/
206
207/* Global memmap only visible to IO MEM module */
208
209#ifdef IxOsalIoMem_C
210
211IxOsalMemoryMap ixOsalGlobalMemoryMap[] = {
212 {
213 /* Global BE and LE_AC map */
214 IX_OSAL_STATIC_MAP, /* type */
215 0x00000000, /* physicalAddress */
216 0x30000000, /* size */
217 0x00000000, /* virtualAddress */
218 NULL, /* mapFunction */
219 NULL, /* unmapFunction */
220 0, /* refCount */
221 IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
222 "global_low" /* name */
223 },
224
225 /* SDRAM LE_DC alias */
226 {
227 IX_OSAL_STATIC_MAP, /* type */
228 0x00000000, /* physicalAddress */
229 0x10000000, /* size */
230 0x30000000, /* virtualAddress */
231 NULL, /* mapFunction */
232 NULL, /* unmapFunction */
233 0, /* refCount */
234 IX_OSAL_LE_DC, /* endianType */
235 "sdram_dc" /* name */
236 },
237
238 /* QMGR LE_DC alias */
239 {
240 IX_OSAL_STATIC_MAP, /* type */
241 0x60000000, /* physicalAddress */
242 0x00100000, /* size */
243 0x60000000, /* virtualAddress */
244 NULL, /* mapFunction */
245 NULL, /* unmapFunction */
246 0, /* refCount */
247 IX_OSAL_LE_DC, /* endianType */
248 "qmgr_dc" /* name */
249 },
250
251 /* QMGR BE alias */
252 {
253 IX_OSAL_STATIC_MAP, /* type */
254 0x60000000, /* physicalAddress */
255 0x00100000, /* size */
256 0x60000000, /* virtualAddress */
257 NULL, /* mapFunction */
258 NULL, /* unmapFunction */
259 0, /* refCount */
260 IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
261 "qmgr_be" /* name */
262 },
263
264 /* Global BE and LE_AC map */
265 {
266 IX_OSAL_STATIC_MAP, /* type */
267 0x40000000, /* physicalAddress */
268 0x20000000, /* size */
269 0x40000000, /* virtualAddress */
270 NULL, /* mapFunction */
271 NULL, /* unmapFunction */
272 0, /* refCount */
273 IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
274 "Misc Cfg" /* name */
275 },
276
277 /* Global BE and LE_AC map */
278 {
279 IX_OSAL_STATIC_MAP, /* type */
280 0x70000000, /* physicalAddress */
281 0x8FFFFFFF, /* size */
282 0x70000000, /* virtualAddress */
283 NULL, /* mapFunction */
284 NULL, /* unmapFunction */
285 0, /* refCount */
286 IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
287 "Exp Cfg" /* name */
288 },
289};
290
291#endif /* IxOsalIoMem_C */
292#endif /* #define IxOsalOsIxp400_H */