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wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2001
3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Date & Time support for ST Electronics M48T35Ax RTC
26 */
27
28/*#define DEBUG */
29
30
31#include <common.h>
32#include <command.h>
33#include <rtc.h>
34#include <config.h>
35
Michal Simekc3e6c552008-07-14 19:45:37 +020036#if defined(CONFIG_CMD_DATE)
wdenkaffae2b2002-08-17 09:36:01 +000037
38static uchar rtc_read (uchar reg);
39static void rtc_write (uchar reg, uchar val);
wdenkaffae2b2002-08-17 09:36:01 +000040
41/* ------------------------------------------------------------------------- */
42
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030043int rtc_get (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +000044{
45 uchar sec, min, hour, cent_day, date, month, year;
46 uchar ccr; /* Clock control register */
47
48 /* Lock RTC for read using clock control register */
49 ccr = rtc_read(0);
50 ccr = ccr | 0x40;
51 rtc_write(0, ccr);
52
53 sec = rtc_read (0x1);
54 min = rtc_read (0x2);
55 hour = rtc_read (0x3);
56 cent_day= rtc_read (0x4);
57 date = rtc_read (0x5);
58 month = rtc_read (0x6);
59 year = rtc_read (0x7);
60
61 /* UNLock RTC */
62 ccr = rtc_read(0);
63 ccr = ccr & 0xBF;
64 rtc_write(0, ccr);
65
66 debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x "
67 "hr: %02x min: %02x sec: %02x\n",
68 year, month, date, cent_day,
69 hour, min, sec );
70
71 tmp->tm_sec = bcd2bin (sec & 0x7F);
72 tmp->tm_min = bcd2bin (min & 0x7F);
73 tmp->tm_hour = bcd2bin (hour & 0x3F);
74 tmp->tm_mday = bcd2bin (date & 0x3F);
75 tmp->tm_mon = bcd2bin (month & 0x1F);
76 tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900);
77 tmp->tm_wday = bcd2bin (cent_day & 0x07);
78 tmp->tm_yday = 0;
79 tmp->tm_isdst= 0;
80
81 debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
82 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
83 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030084
85 return 0;
wdenkaffae2b2002-08-17 09:36:01 +000086}
87
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +020088int rtc_set (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +000089{
90 uchar ccr; /* Clock control register */
91 uchar century;
92
93 debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
94 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
95 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
96
97 /* Lock RTC for write using clock control register */
98 ccr = rtc_read(0);
99 ccr = ccr | 0x80;
100 rtc_write(0, ccr);
101
102 rtc_write (0x07, bin2bcd(tmp->tm_year % 100));
103 rtc_write (0x06, bin2bcd(tmp->tm_mon));
104 rtc_write (0x05, bin2bcd(tmp->tm_mday));
105
106 century = ((tmp->tm_year >= 2000) ? 0x10 : 0) | 0x20;
107 rtc_write (0x04, bin2bcd(tmp->tm_wday) | century);
108
109 rtc_write (0x03, bin2bcd(tmp->tm_hour));
110 rtc_write (0x02, bin2bcd(tmp->tm_min ));
111 rtc_write (0x01, bin2bcd(tmp->tm_sec ));
112
113 /* UNLock RTC */
114 ccr = rtc_read(0);
115 ccr = ccr & 0x7F;
116 rtc_write(0, ccr);
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200117
118 return 0;
wdenkaffae2b2002-08-17 09:36:01 +0000119}
120
121void rtc_reset (void)
122{
123 uchar val;
124
125 /* Clear all clock control registers */
126 rtc_write (0x0, 0x80); /* No Read Lock or calibration */
127
128 /* Clear stop bit */
129 val = rtc_read (0x1);
130 val &= 0x7f;
131 rtc_write(0x1, val);
132
133 /* Enable century / disable frequency test */
134 val = rtc_read (0x4);
135 val = (val & 0xBF) | 0x20;
136 rtc_write(0x4, val);
137
138 /* Clear write lock */
139 rtc_write(0x0, 0);
140}
141
142/* ------------------------------------------------------------------------- */
143
144static uchar rtc_read (uchar reg)
145{
146 uchar val;
147 val = *(unsigned char *)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148 ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg);
wdenkaffae2b2002-08-17 09:36:01 +0000149 return val;
150}
151
152static void rtc_write (uchar reg, uchar val)
153{
154 *(unsigned char *)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155 ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val;
wdenkaffae2b2002-08-17 09:36:01 +0000156}
157
Jon Loeliger07efe2a2007-07-10 10:27:39 -0500158#endif