blob: 970ee1adf1ba406a30e4c5fa7e15e59b8e6d2c10 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassb94dc892015-03-05 12:25:25 -07002/*
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
Simon Glassb94dc892015-03-05 12:25:25 -07005 */
6
Patrick Delaunay81313352021-04-27 11:02:19 +02007#define LOG_CATEGORY UCLASS_PCI
8
Simon Glassb94dc892015-03-05 12:25:25 -07009#include <common.h>
10#include <dm.h>
11#include <errno.h>
Simon Glass97589732020-05-10 11:40:02 -060012#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070014#include <malloc.h>
Simon Glassb94dc892015-03-05 12:25:25 -070015#include <pci.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
Simon Glassc5f053b2015-11-29 13:18:03 -070017#include <asm/io.h>
Simon Glassb94dc892015-03-05 12:25:25 -070018#include <dm/device-internal.h>
Simon Glass89d83232017-05-18 20:09:51 -060019#include <dm/lists.h>
Simon Glassbe706102020-12-16 21:20:18 -070020#include <dm/uclass-internal.h>
Bin Mengc0820a42015-08-20 06:40:23 -070021#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
Simon Glassef8a2dd2019-08-24 14:19:05 -060022#include <asm/fsp/fsp_support.h>
Bin Mengc0820a42015-08-20 06:40:23 -070023#endif
Simon Glass8807a562021-06-27 17:50:57 -060024#include <dt-bindings/pci/pci.h>
Simon Glassdbd79542020-05-10 11:40:11 -060025#include <linux/delay.h>
Simon Glass37a3f94b2015-11-29 13:17:49 -070026#include "pci_internal.h"
Simon Glassb94dc892015-03-05 12:25:25 -070027
28DECLARE_GLOBAL_DATA_PTR;
29
Simon Glass2e4e4432016-01-18 20:19:14 -070030int pci_get_bus(int busnum, struct udevice **busp)
Simon Glass7d07e592015-08-31 18:55:35 -060031{
32 int ret;
33
34 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
35
36 /* Since buses may not be numbered yet try a little harder with bus 0 */
37 if (ret == -ENODEV) {
Simon Glassc7298e72016-02-11 13:23:26 -070038 ret = uclass_first_device_err(UCLASS_PCI, busp);
Simon Glass7d07e592015-08-31 18:55:35 -060039 if (ret)
40 return ret;
Simon Glass7d07e592015-08-31 18:55:35 -060041 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
42 }
43
44 return ret;
45}
46
Simon Glass6256d672015-11-19 20:27:00 -070047struct udevice *pci_get_controller(struct udevice *dev)
48{
49 while (device_is_on_pci_bus(dev))
50 dev = dev->parent;
51
52 return dev;
53}
54
Simon Glassc92aac12020-01-27 08:49:38 -070055pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
Simon Glassc9118d42015-07-06 16:47:46 -060056{
Simon Glassb75b15b2020-12-03 16:55:23 -070057 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
Simon Glassc9118d42015-07-06 16:47:46 -060058 struct udevice *bus = dev->parent;
59
Simon Glass1c6449c2019-12-29 21:19:14 -070060 /*
61 * This error indicates that @dev is a device on an unprobed PCI bus.
62 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
63 * will produce a bad BDF>
64 *
65 * A common cause of this problem is that this function is called in the
Simon Glassaad29ae2020-12-03 16:55:21 -070066 * of_to_plat() method of @dev. Accessing the PCI bus in that
Simon Glass1c6449c2019-12-29 21:19:14 -070067 * method is not allowed, since it has not yet been probed. To fix this,
68 * move that access to the probe() method of @dev instead.
69 */
70 if (!device_active(bus))
71 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
72 bus->name);
Simon Glass75e534b2020-12-16 21:20:07 -070073 return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
Simon Glassc9118d42015-07-06 16:47:46 -060074}
75
Simon Glassb94dc892015-03-05 12:25:25 -070076/**
77 * pci_get_bus_max() - returns the bus number of the last active bus
78 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010079 * Return: last bus number, or -1 if no active buses
Simon Glassb94dc892015-03-05 12:25:25 -070080 */
81static int pci_get_bus_max(void)
82{
83 struct udevice *bus;
84 struct uclass *uc;
85 int ret = -1;
86
87 ret = uclass_get(UCLASS_PCI, &uc);
88 uclass_foreach_dev(bus, uc) {
Simon Glass75e534b2020-12-16 21:20:07 -070089 if (dev_seq(bus) > ret)
90 ret = dev_seq(bus);
Simon Glassb94dc892015-03-05 12:25:25 -070091 }
92
93 debug("%s: ret=%d\n", __func__, ret);
94
95 return ret;
96}
97
98int pci_last_busno(void)
99{
Bin Meng5bc3f8a2015-10-01 00:36:01 -0700100 return pci_get_bus_max();
Simon Glassb94dc892015-03-05 12:25:25 -0700101}
102
103int pci_get_ff(enum pci_size_t size)
104{
105 switch (size) {
106 case PCI_SIZE_8:
107 return 0xff;
108 case PCI_SIZE_16:
109 return 0xffff;
110 default:
111 return 0xffffffff;
112 }
113}
114
Marek Vasutb4535792018-10-10 21:27:06 +0200115static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
116 ofnode *rnode)
117{
118 struct fdt_pci_addr addr;
119 ofnode node;
120 int ret;
121
122 dev_for_each_subnode(node, bus) {
123 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
124 &addr);
125 if (ret)
126 continue;
127
128 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
129 continue;
130
131 *rnode = node;
132 break;
133 }
134};
135
Simon Glass2a311e82020-01-27 08:49:37 -0700136int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
Simon Glassb94dc892015-03-05 12:25:25 -0700137 struct udevice **devp)
138{
139 struct udevice *dev;
140
141 for (device_find_first_child(bus, &dev);
142 dev;
143 device_find_next_child(&dev)) {
Simon Glassb75b15b2020-12-03 16:55:23 -0700144 struct pci_child_plat *pplat;
Simon Glassb94dc892015-03-05 12:25:25 -0700145
Simon Glass71fa5b42020-12-03 16:55:18 -0700146 pplat = dev_get_parent_plat(dev);
Simon Glassb94dc892015-03-05 12:25:25 -0700147 if (pplat && pplat->devfn == find_devfn) {
148 *devp = dev;
149 return 0;
150 }
151 }
152
153 return -ENODEV;
154}
155
Simon Glass84283d52015-11-29 13:17:48 -0700156int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
Simon Glassb94dc892015-03-05 12:25:25 -0700157{
158 struct udevice *bus;
159 int ret;
160
Simon Glass7d07e592015-08-31 18:55:35 -0600161 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700162 if (ret)
163 return ret;
164 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
165}
166
167static int pci_device_matches_ids(struct udevice *dev,
Simon Glass3f7dc6e2021-06-27 17:50:56 -0600168 const struct pci_device_id *ids)
Simon Glassb94dc892015-03-05 12:25:25 -0700169{
Simon Glassb75b15b2020-12-03 16:55:23 -0700170 struct pci_child_plat *pplat;
Simon Glassb94dc892015-03-05 12:25:25 -0700171 int i;
172
Simon Glass71fa5b42020-12-03 16:55:18 -0700173 pplat = dev_get_parent_plat(dev);
Simon Glassb94dc892015-03-05 12:25:25 -0700174 if (!pplat)
175 return -EINVAL;
176 for (i = 0; ids[i].vendor != 0; i++) {
177 if (pplat->vendor == ids[i].vendor &&
178 pplat->device == ids[i].device)
179 return i;
180 }
181
182 return -EINVAL;
183}
184
Simon Glass3f7dc6e2021-06-27 17:50:56 -0600185int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
Simon Glassb94dc892015-03-05 12:25:25 -0700186 int *indexp, struct udevice **devp)
187{
188 struct udevice *dev;
189
190 /* Scan all devices on this bus */
191 for (device_find_first_child(bus, &dev);
192 dev;
193 device_find_next_child(&dev)) {
194 if (pci_device_matches_ids(dev, ids) >= 0) {
195 if ((*indexp)-- <= 0) {
196 *devp = dev;
197 return 0;
198 }
199 }
200 }
201
202 return -ENODEV;
203}
204
Simon Glass3f7dc6e2021-06-27 17:50:56 -0600205int pci_find_device_id(const struct pci_device_id *ids, int index,
Simon Glassb94dc892015-03-05 12:25:25 -0700206 struct udevice **devp)
207{
208 struct udevice *bus;
209
210 /* Scan all known buses */
211 for (uclass_first_device(UCLASS_PCI, &bus);
212 bus;
213 uclass_next_device(&bus)) {
214 if (!pci_bus_find_devices(bus, ids, &index, devp))
215 return 0;
216 }
217 *devp = NULL;
218
219 return -ENODEV;
220}
221
Simon Glass70e0c582015-11-29 13:17:50 -0700222static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
223 unsigned int device, int *indexp,
224 struct udevice **devp)
225{
Simon Glassb75b15b2020-12-03 16:55:23 -0700226 struct pci_child_plat *pplat;
Simon Glass70e0c582015-11-29 13:17:50 -0700227 struct udevice *dev;
228
229 for (device_find_first_child(bus, &dev);
230 dev;
231 device_find_next_child(&dev)) {
Simon Glass71fa5b42020-12-03 16:55:18 -0700232 pplat = dev_get_parent_plat(dev);
Simon Glass70e0c582015-11-29 13:17:50 -0700233 if (pplat->vendor == vendor && pplat->device == device) {
234 if (!(*indexp)--) {
235 *devp = dev;
236 return 0;
237 }
238 }
239 }
240
241 return -ENODEV;
242}
243
244int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
245 struct udevice **devp)
246{
247 struct udevice *bus;
248
249 /* Scan all known buses */
250 for (uclass_first_device(UCLASS_PCI, &bus);
251 bus;
252 uclass_next_device(&bus)) {
253 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
254 return device_probe(*devp);
255 }
256 *devp = NULL;
257
258 return -ENODEV;
259}
260
Simon Glassb639d512015-11-29 13:17:52 -0700261int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
262{
263 struct udevice *dev;
264
265 /* Scan all known buses */
266 for (pci_find_first_device(&dev);
267 dev;
268 pci_find_next_device(&dev)) {
Simon Glassb75b15b2020-12-03 16:55:23 -0700269 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
Simon Glassb639d512015-11-29 13:17:52 -0700270
271 if (pplat->class == find_class && !index--) {
272 *devp = dev;
273 return device_probe(*devp);
274 }
275 }
276 *devp = NULL;
277
278 return -ENODEV;
279}
280
Simon Glassb94dc892015-03-05 12:25:25 -0700281int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
282 unsigned long value, enum pci_size_t size)
283{
284 struct dm_pci_ops *ops;
285
286 ops = pci_get_ops(bus);
287 if (!ops->write_config)
288 return -ENOSYS;
289 return ops->write_config(bus, bdf, offset, value, size);
290}
291
Simon Glass9cec2df2016-03-06 19:27:52 -0700292int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
293 u32 clr, u32 set)
294{
295 ulong val;
296 int ret;
297
298 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
299 if (ret)
300 return ret;
301 val &= ~clr;
302 val |= set;
303
304 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
305}
306
Vladimir Oltean278a5b52021-09-17 15:11:25 +0300307static int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
308 enum pci_size_t size)
Simon Glassb94dc892015-03-05 12:25:25 -0700309{
310 struct udevice *bus;
311 int ret;
312
Simon Glass7d07e592015-08-31 18:55:35 -0600313 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700314 if (ret)
315 return ret;
316
Bin Meng0a721522015-07-19 00:20:04 +0800317 return pci_bus_write_config(bus, bdf, offset, value, size);
Simon Glassb94dc892015-03-05 12:25:25 -0700318}
319
Simon Glass94ef2422015-08-10 07:05:03 -0600320int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
321 enum pci_size_t size)
322{
323 struct udevice *bus;
324
Bin Meng05bedb12015-09-11 03:24:34 -0700325 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass94ef2422015-08-10 07:05:03 -0600326 bus = bus->parent;
Simon Glasseaa14892015-11-29 13:17:47 -0700327 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
328 size);
Simon Glass94ef2422015-08-10 07:05:03 -0600329}
330
Simon Glassb94dc892015-03-05 12:25:25 -0700331int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
332{
333 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
334}
335
336int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
337{
338 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
339}
340
341int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
342{
343 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
344}
345
Simon Glass94ef2422015-08-10 07:05:03 -0600346int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
347{
348 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
349}
350
351int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
352{
353 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
354}
355
356int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
357{
358 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
359}
360
Simon Glassc92aac12020-01-27 08:49:38 -0700361int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
Simon Glassb94dc892015-03-05 12:25:25 -0700362 unsigned long *valuep, enum pci_size_t size)
363{
364 struct dm_pci_ops *ops;
365
366 ops = pci_get_ops(bus);
367 if (!ops->read_config)
368 return -ENOSYS;
369 return ops->read_config(bus, bdf, offset, valuep, size);
370}
371
Vladimir Oltean69c5f8a2021-09-17 15:11:26 +0300372static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
373 enum pci_size_t size)
Simon Glassb94dc892015-03-05 12:25:25 -0700374{
375 struct udevice *bus;
376 int ret;
377
Simon Glass7d07e592015-08-31 18:55:35 -0600378 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700379 if (ret)
380 return ret;
381
Bin Meng0a721522015-07-19 00:20:04 +0800382 return pci_bus_read_config(bus, bdf, offset, valuep, size);
Simon Glassb94dc892015-03-05 12:25:25 -0700383}
384
Simon Glassc92aac12020-01-27 08:49:38 -0700385int dm_pci_read_config(const struct udevice *dev, int offset,
386 unsigned long *valuep, enum pci_size_t size)
Simon Glass94ef2422015-08-10 07:05:03 -0600387{
Simon Glassc92aac12020-01-27 08:49:38 -0700388 const struct udevice *bus;
Simon Glass94ef2422015-08-10 07:05:03 -0600389
Bin Meng05bedb12015-09-11 03:24:34 -0700390 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass94ef2422015-08-10 07:05:03 -0600391 bus = bus->parent;
Simon Glasseaa14892015-11-29 13:17:47 -0700392 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
Simon Glass94ef2422015-08-10 07:05:03 -0600393 size);
394}
395
Simon Glassb94dc892015-03-05 12:25:25 -0700396int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
397{
398 unsigned long value;
399 int ret;
400
401 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
402 if (ret)
403 return ret;
404 *valuep = value;
405
406 return 0;
407}
408
409int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
410{
411 unsigned long value;
412 int ret;
413
414 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
415 if (ret)
416 return ret;
417 *valuep = value;
418
419 return 0;
420}
421
422int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
423{
424 unsigned long value;
425 int ret;
426
427 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
428 if (ret)
429 return ret;
430 *valuep = value;
431
432 return 0;
433}
434
Simon Glassc92aac12020-01-27 08:49:38 -0700435int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
Simon Glass94ef2422015-08-10 07:05:03 -0600436{
437 unsigned long value;
438 int ret;
439
440 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
441 if (ret)
442 return ret;
443 *valuep = value;
444
445 return 0;
446}
447
Simon Glassc92aac12020-01-27 08:49:38 -0700448int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
Simon Glass94ef2422015-08-10 07:05:03 -0600449{
450 unsigned long value;
451 int ret;
452
453 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
454 if (ret)
455 return ret;
456 *valuep = value;
457
458 return 0;
459}
460
Simon Glassc92aac12020-01-27 08:49:38 -0700461int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
Simon Glass94ef2422015-08-10 07:05:03 -0600462{
463 unsigned long value;
464 int ret;
465
466 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
467 if (ret)
468 return ret;
469 *valuep = value;
470
471 return 0;
472}
473
Simon Glass9cec2df2016-03-06 19:27:52 -0700474int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
475{
476 u8 val;
477 int ret;
478
479 ret = dm_pci_read_config8(dev, offset, &val);
480 if (ret)
481 return ret;
482 val &= ~clr;
483 val |= set;
484
485 return dm_pci_write_config8(dev, offset, val);
486}
487
488int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
489{
490 u16 val;
491 int ret;
492
493 ret = dm_pci_read_config16(dev, offset, &val);
494 if (ret)
495 return ret;
496 val &= ~clr;
497 val |= set;
498
499 return dm_pci_write_config16(dev, offset, val);
500}
501
502int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
503{
504 u32 val;
505 int ret;
506
507 ret = dm_pci_read_config32(dev, offset, &val);
508 if (ret)
509 return ret;
510 val &= ~clr;
511 val |= set;
512
513 return dm_pci_write_config32(dev, offset, val);
514}
515
Bin Menga0705782015-10-01 00:36:02 -0700516static void set_vga_bridge_bits(struct udevice *dev)
517{
518 struct udevice *parent = dev->parent;
519 u16 bc;
520
Simon Glass75e534b2020-12-16 21:20:07 -0700521 while (dev_seq(parent) != 0) {
Bin Menga0705782015-10-01 00:36:02 -0700522 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
523 bc |= PCI_BRIDGE_CTL_VGA;
524 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
525 parent = parent->parent;
526 }
527}
528
Simon Glassb94dc892015-03-05 12:25:25 -0700529int pci_auto_config_devices(struct udevice *bus)
530{
Simon Glass95588622020-12-22 19:30:28 -0700531 struct pci_controller *hose = dev_get_uclass_priv(bus);
Simon Glassb75b15b2020-12-03 16:55:23 -0700532 struct pci_child_plat *pplat;
Simon Glassb94dc892015-03-05 12:25:25 -0700533 unsigned int sub_bus;
534 struct udevice *dev;
535 int ret;
536
Simon Glass75e534b2020-12-16 21:20:07 -0700537 sub_bus = dev_seq(bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700538 debug("%s: start\n", __func__);
539 pciauto_config_init(hose);
540 for (ret = device_find_first_child(bus, &dev);
541 !ret && dev;
542 ret = device_find_next_child(&dev)) {
Simon Glassb94dc892015-03-05 12:25:25 -0700543 unsigned int max_bus;
Simon Glassb072d522015-09-08 17:52:47 -0600544 int ret;
Simon Glassb94dc892015-03-05 12:25:25 -0700545
Simon Glassb94dc892015-03-05 12:25:25 -0700546 debug("%s: device %s\n", __func__, dev->name);
Simon Glassf1d50f72020-12-19 10:40:13 -0700547 if (dev_has_ofnode(dev) &&
Suneel Garapatif8c86282020-05-04 21:25:25 -0700548 dev_read_bool(dev, "pci,no-autoconfig"))
Simon Glassf3005fb2020-04-08 16:57:26 -0600549 continue;
Simon Glass37a3f94b2015-11-29 13:17:49 -0700550 ret = dm_pciauto_config_device(dev);
Simon Glassb072d522015-09-08 17:52:47 -0600551 if (ret < 0)
Simon Glassbe706102020-12-16 21:20:18 -0700552 return log_msg_ret("auto", ret);
Simon Glassb072d522015-09-08 17:52:47 -0600553 max_bus = ret;
Simon Glassb94dc892015-03-05 12:25:25 -0700554 sub_bus = max(sub_bus, max_bus);
Bin Menga0705782015-10-01 00:36:02 -0700555
Masami Hiramatsu7ccdc672021-06-04 18:43:34 +0900556 if (dev_get_parent(dev) == bus)
557 continue;
558
Simon Glass71fa5b42020-12-03 16:55:18 -0700559 pplat = dev_get_parent_plat(dev);
Bin Menga0705782015-10-01 00:36:02 -0700560 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
561 set_vga_bridge_bits(dev);
Simon Glassb94dc892015-03-05 12:25:25 -0700562 }
Pali RohĂĄr8b79e082022-01-17 16:38:37 +0100563 if (hose->last_busno < sub_bus)
564 hose->last_busno = sub_bus;
Simon Glassb94dc892015-03-05 12:25:25 -0700565 debug("%s: done\n", __func__);
566
Simon Glassbe706102020-12-16 21:20:18 -0700567 return log_msg_ret("sub", sub_bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700568}
569
Tuomas Tynkkynen8cce4cf2017-09-19 23:18:03 +0300570int pci_generic_mmap_write_config(
Simon Glass2a311e82020-01-27 08:49:37 -0700571 const struct udevice *bus,
572 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
573 void **addrp),
Tuomas Tynkkynen8cce4cf2017-09-19 23:18:03 +0300574 pci_dev_t bdf,
575 uint offset,
576 ulong value,
577 enum pci_size_t size)
578{
579 void *address;
580
581 if (addr_f(bus, bdf, offset, &address) < 0)
582 return 0;
583
584 switch (size) {
585 case PCI_SIZE_8:
586 writeb(value, address);
587 return 0;
588 case PCI_SIZE_16:
589 writew(value, address);
590 return 0;
591 case PCI_SIZE_32:
592 writel(value, address);
593 return 0;
594 default:
595 return -EINVAL;
596 }
597}
598
599int pci_generic_mmap_read_config(
Simon Glass2a311e82020-01-27 08:49:37 -0700600 const struct udevice *bus,
601 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
602 void **addrp),
Tuomas Tynkkynen8cce4cf2017-09-19 23:18:03 +0300603 pci_dev_t bdf,
604 uint offset,
605 ulong *valuep,
606 enum pci_size_t size)
607{
608 void *address;
609
610 if (addr_f(bus, bdf, offset, &address) < 0) {
611 *valuep = pci_get_ff(size);
612 return 0;
613 }
614
615 switch (size) {
616 case PCI_SIZE_8:
617 *valuep = readb(address);
618 return 0;
619 case PCI_SIZE_16:
620 *valuep = readw(address);
621 return 0;
622 case PCI_SIZE_32:
623 *valuep = readl(address);
624 return 0;
625 default:
626 return -EINVAL;
627 }
628}
629
Simon Glass37a3f94b2015-11-29 13:17:49 -0700630int dm_pci_hose_probe_bus(struct udevice *bus)
Simon Glassb94dc892015-03-05 12:25:25 -0700631{
Pali RohĂĄr4fb65992021-10-07 14:50:58 +0200632 u8 header_type;
Simon Glassb94dc892015-03-05 12:25:25 -0700633 int sub_bus;
634 int ret;
Suneel Garapati1b9c44e2019-10-19 15:52:32 -0700635 int ea_pos;
636 u8 reg;
Simon Glassb94dc892015-03-05 12:25:25 -0700637
638 debug("%s\n", __func__);
Simon Glassb94dc892015-03-05 12:25:25 -0700639
Pali RohĂĄr4fb65992021-10-07 14:50:58 +0200640 dm_pci_read_config8(bus, PCI_HEADER_TYPE, &header_type);
641 header_type &= 0x7f;
642 if (header_type != PCI_HEADER_TYPE_BRIDGE) {
643 debug("%s: Skipping PCI device %d with Non-Bridge Header Type 0x%x\n",
644 __func__, PCI_DEV(dm_pci_get_bdf(bus)), header_type);
645 return log_msg_ret("probe", -EINVAL);
646 }
647
Andrew Scull71e7e1a2022-04-21 16:11:16 +0000648 if (IS_ENABLED(CONFIG_PCI_ENHANCED_ALLOCATION))
649 ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
650 else
651 ea_pos = 0;
652
Suneel Garapati1b9c44e2019-10-19 15:52:32 -0700653 if (ea_pos) {
654 dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
655 &reg);
656 sub_bus = reg;
657 } else {
658 sub_bus = pci_get_bus_max() + 1;
659 }
Simon Glassb94dc892015-03-05 12:25:25 -0700660 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
Simon Glass37a3f94b2015-11-29 13:17:49 -0700661 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700662
663 ret = device_probe(bus);
664 if (ret) {
Simon Glass3b02d842015-09-08 17:52:48 -0600665 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
Simon Glassb94dc892015-03-05 12:25:25 -0700666 ret);
Simon Glassbe706102020-12-16 21:20:18 -0700667 return log_msg_ret("probe", ret);
Simon Glassb94dc892015-03-05 12:25:25 -0700668 }
Suneel Garapati1b9c44e2019-10-19 15:52:32 -0700669
Masami Hiramatsuff022452021-04-16 14:53:46 -0700670 if (!ea_pos)
671 sub_bus = pci_get_bus_max();
672
Simon Glass37a3f94b2015-11-29 13:17:49 -0700673 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700674
675 return sub_bus;
676}
677
Simon Glass318d71c2015-07-06 16:47:44 -0600678/**
679 * pci_match_one_device - Tell if a PCI device structure has a matching
680 * PCI device id structure
681 * @id: single PCI device id structure to match
Hou Zhiqiangd19d0612017-03-22 16:07:24 +0800682 * @find: the PCI device id structure to match against
Simon Glass318d71c2015-07-06 16:47:44 -0600683 *
Hou Zhiqiangd19d0612017-03-22 16:07:24 +0800684 * Returns true if the finding pci_device_id structure matched or false if
685 * there is no match.
Simon Glass318d71c2015-07-06 16:47:44 -0600686 */
687static bool pci_match_one_id(const struct pci_device_id *id,
688 const struct pci_device_id *find)
689{
690 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
691 (id->device == PCI_ANY_ID || id->device == find->device) &&
692 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
693 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
694 !((id->class ^ find->class) & id->class_mask))
695 return true;
696
697 return false;
698}
699
700/**
Simon Glass8807a562021-06-27 17:50:57 -0600701 * pci_need_device_pre_reloc() - Check if a device should be bound
702 *
703 * This checks a list of vendor/device-ID values indicating devices that should
704 * be bound before relocation.
705 *
706 * @bus: Bus to check
707 * @vendor: Vendor ID to check
708 * @device: Device ID to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100709 * Return: true if the vendor/device is in the list, false if not
Simon Glass8807a562021-06-27 17:50:57 -0600710 */
711static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor,
712 uint device)
713{
714 u32 vendev;
715 int index;
716
717 for (index = 0;
718 !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index,
719 &vendev);
720 index++) {
721 if (vendev == PCI_VENDEV(vendor, device))
722 return true;
723 }
724
725 return false;
726}
727
728/**
Simon Glass318d71c2015-07-06 16:47:44 -0600729 * pci_find_and_bind_driver() - Find and bind the right PCI driver
730 *
731 * This only looks at certain fields in the descriptor.
Simon Glassc45abf12015-09-08 17:52:49 -0600732 *
733 * @parent: Parent bus
734 * @find_id: Specification of the driver to find
735 * @bdf: Bus/device/function addreess - see PCI_BDF()
736 * @devp: Returns a pointer to the device created
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100737 * Return: 0 if OK, -EPERM if the device is not needed before relocation and
Simon Glassc45abf12015-09-08 17:52:49 -0600738 * therefore was not created, other -ve value on error
Simon Glass318d71c2015-07-06 16:47:44 -0600739 */
740static int pci_find_and_bind_driver(struct udevice *parent,
Simon Glassc45abf12015-09-08 17:52:49 -0600741 struct pci_device_id *find_id,
742 pci_dev_t bdf, struct udevice **devp)
Simon Glass318d71c2015-07-06 16:47:44 -0600743{
744 struct pci_driver_entry *start, *entry;
Marek Vasutb4535792018-10-10 21:27:06 +0200745 ofnode node = ofnode_null();
Simon Glass318d71c2015-07-06 16:47:44 -0600746 const char *drv;
747 int n_ents;
748 int ret;
749 char name[30], *str;
Bin Meng984c0dc2015-08-20 06:40:17 -0700750 bool bridge;
Simon Glass318d71c2015-07-06 16:47:44 -0600751
752 *devp = NULL;
753
754 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
755 find_id->vendor, find_id->device);
Marek Vasutb4535792018-10-10 21:27:06 +0200756
757 /* Determine optional OF node */
Suneel Garapaticb7093d2019-10-19 16:02:48 -0700758 if (ofnode_valid(dev_ofnode(parent)))
759 pci_dev_find_ofnode(parent, bdf, &node);
Marek Vasutb4535792018-10-10 21:27:06 +0200760
Michael Walle2e21f372019-12-01 17:45:18 +0100761 if (ofnode_valid(node) && !ofnode_is_available(node)) {
762 debug("%s: Ignoring disabled device\n", __func__);
Simon Glassbe706102020-12-16 21:20:18 -0700763 return log_msg_ret("dis", -EPERM);
Michael Walle2e21f372019-12-01 17:45:18 +0100764 }
765
Simon Glass318d71c2015-07-06 16:47:44 -0600766 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
767 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
768 for (entry = start; entry != start + n_ents; entry++) {
769 const struct pci_device_id *id;
770 struct udevice *dev;
771 const struct driver *drv;
772
773 for (id = entry->match;
774 id->vendor || id->subvendor || id->class_mask;
775 id++) {
776 if (!pci_match_one_id(id, find_id))
777 continue;
778
779 drv = entry->driver;
Bin Meng984c0dc2015-08-20 06:40:17 -0700780
781 /*
782 * In the pre-relocation phase, we only bind devices
783 * whose driver has the DM_FLAG_PRE_RELOC set, to save
784 * precious memory space as on some platforms as that
785 * space is pretty limited (ie: using Cache As RAM).
786 */
787 if (!(gd->flags & GD_FLG_RELOC) &&
788 !(drv->flags & DM_FLAG_PRE_RELOC))
Simon Glassbe706102020-12-16 21:20:18 -0700789 return log_msg_ret("pre", -EPERM);
Bin Meng984c0dc2015-08-20 06:40:17 -0700790
Simon Glass318d71c2015-07-06 16:47:44 -0600791 /*
792 * We could pass the descriptor to the driver as
Simon Glass71fa5b42020-12-03 16:55:18 -0700793 * plat (instead of NULL) and allow its bind()
Simon Glass318d71c2015-07-06 16:47:44 -0600794 * method to return -ENOENT if it doesn't support this
795 * device. That way we could continue the search to
796 * find another driver. For now this doesn't seem
797 * necesssary, so just bind the first match.
798 */
Simon Glass884870f2020-11-28 17:50:01 -0700799 ret = device_bind(parent, drv, drv->name, NULL, node,
800 &dev);
Simon Glass318d71c2015-07-06 16:47:44 -0600801 if (ret)
802 goto error;
803 debug("%s: Match found: %s\n", __func__, drv->name);
Bin Menga8d27802018-08-03 01:14:44 -0700804 dev->driver_data = id->driver_data;
Simon Glass318d71c2015-07-06 16:47:44 -0600805 *devp = dev;
806 return 0;
807 }
808 }
809
Bin Meng984c0dc2015-08-20 06:40:17 -0700810 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
811 /*
812 * In the pre-relocation phase, we only bind bridge devices to save
813 * precious memory space as on some platforms as that space is pretty
814 * limited (ie: using Cache As RAM).
815 */
Simon Glass8807a562021-06-27 17:50:57 -0600816 if (!(gd->flags & GD_FLG_RELOC) && !bridge &&
817 !pci_need_device_pre_reloc(parent, find_id->vendor,
818 find_id->device))
Simon Glassbe706102020-12-16 21:20:18 -0700819 return log_msg_ret("notbr", -EPERM);
Bin Meng984c0dc2015-08-20 06:40:17 -0700820
Simon Glass318d71c2015-07-06 16:47:44 -0600821 /* Bind a generic driver so that the device can be used */
Simon Glass75e534b2020-12-16 21:20:07 -0700822 sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
Bin Meng0a721522015-07-19 00:20:04 +0800823 PCI_FUNC(bdf));
Simon Glass318d71c2015-07-06 16:47:44 -0600824 str = strdup(name);
825 if (!str)
826 return -ENOMEM;
Bin Meng984c0dc2015-08-20 06:40:17 -0700827 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
828
Marek Vasutb4535792018-10-10 21:27:06 +0200829 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
Simon Glass318d71c2015-07-06 16:47:44 -0600830 if (ret) {
Simon Glass3b02d842015-09-08 17:52:48 -0600831 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
xypron.glpk@gmx.dea89009c2017-05-08 20:40:16 +0200832 free(str);
Simon Glass318d71c2015-07-06 16:47:44 -0600833 return ret;
834 }
835 debug("%s: No match found: bound generic driver instead\n", __func__);
836
837 return 0;
838
839error:
840 debug("%s: No match found: error %d\n", __func__, ret);
841 return ret;
842}
843
Tim Harvey4c57bf72021-04-16 14:53:47 -0700844__weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
845{
846}
847
Simon Glassb94dc892015-03-05 12:25:25 -0700848int pci_bind_bus_devices(struct udevice *bus)
849{
850 ulong vendor, device;
851 ulong header_type;
Bin Meng0a721522015-07-19 00:20:04 +0800852 pci_dev_t bdf, end;
Simon Glassb94dc892015-03-05 12:25:25 -0700853 bool found_multi;
Suneel Garapatia99a5eb2019-10-23 18:40:36 -0700854 int ari_off;
Simon Glassb94dc892015-03-05 12:25:25 -0700855 int ret;
856
857 found_multi = false;
Simon Glass75e534b2020-12-16 21:20:07 -0700858 end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
Bin Meng0a721522015-07-19 00:20:04 +0800859 PCI_MAX_PCI_FUNCTIONS - 1);
Simon Glass75e534b2020-12-16 21:20:07 -0700860 for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
Bin Meng0a721522015-07-19 00:20:04 +0800861 bdf += PCI_BDF(0, 0, 1)) {
Simon Glassb75b15b2020-12-03 16:55:23 -0700862 struct pci_child_plat *pplat;
Simon Glassb94dc892015-03-05 12:25:25 -0700863 struct udevice *dev;
864 ulong class;
865
Bin Meng20bdc1e2018-08-03 01:14:37 -0700866 if (!PCI_FUNC(bdf))
867 found_multi = false;
Bin Meng0a721522015-07-19 00:20:04 +0800868 if (PCI_FUNC(bdf) && !found_multi)
Simon Glassb94dc892015-03-05 12:25:25 -0700869 continue;
Hou Zhiqiangfb862b052018-10-08 16:35:47 +0800870
Simon Glassb94dc892015-03-05 12:25:25 -0700871 /* Check only the first access, we don't expect problems */
Hou Zhiqiangfb862b052018-10-08 16:35:47 +0800872 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
873 PCI_SIZE_16);
Pali RohĂĄra8a520d2021-09-07 18:07:08 +0200874 if (ret || vendor == 0xffff || vendor == 0x0000)
Simon Glassb94dc892015-03-05 12:25:25 -0700875 continue;
876
Hou Zhiqiangfb862b052018-10-08 16:35:47 +0800877 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
878 &header_type, PCI_SIZE_8);
879
Bin Meng0a721522015-07-19 00:20:04 +0800880 if (!PCI_FUNC(bdf))
Simon Glassb94dc892015-03-05 12:25:25 -0700881 found_multi = header_type & 0x80;
882
Simon Glass25916d62019-09-25 08:56:12 -0600883 debug("%s: bus %d/%s: found device %x, function %d", __func__,
Simon Glass75e534b2020-12-16 21:20:07 -0700884 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
Bin Meng0a721522015-07-19 00:20:04 +0800885 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
Simon Glassb94dc892015-03-05 12:25:25 -0700886 PCI_SIZE_16);
Bin Meng0a721522015-07-19 00:20:04 +0800887 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
Simon Glass318d71c2015-07-06 16:47:44 -0600888 PCI_SIZE_32);
889 class >>= 8;
Simon Glassb94dc892015-03-05 12:25:25 -0700890
891 /* Find this device in the device tree */
Bin Meng0a721522015-07-19 00:20:04 +0800892 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
Simon Glass25916d62019-09-25 08:56:12 -0600893 debug(": find ret=%d\n", ret);
Simon Glassb94dc892015-03-05 12:25:25 -0700894
Simon Glass413ebdb2015-11-29 13:18:09 -0700895 /* If nothing in the device tree, bind a device */
Simon Glassb94dc892015-03-05 12:25:25 -0700896 if (ret == -ENODEV) {
Simon Glass318d71c2015-07-06 16:47:44 -0600897 struct pci_device_id find_id;
898 ulong val;
Simon Glassb94dc892015-03-05 12:25:25 -0700899
Simon Glass318d71c2015-07-06 16:47:44 -0600900 memset(&find_id, '\0', sizeof(find_id));
901 find_id.vendor = vendor;
902 find_id.device = device;
903 find_id.class = class;
904 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
Bin Meng0a721522015-07-19 00:20:04 +0800905 pci_bus_read_config(bus, bdf,
Simon Glass318d71c2015-07-06 16:47:44 -0600906 PCI_SUBSYSTEM_VENDOR_ID,
907 &val, PCI_SIZE_32);
908 find_id.subvendor = val & 0xffff;
909 find_id.subdevice = val >> 16;
910 }
Bin Meng0a721522015-07-19 00:20:04 +0800911 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
Simon Glass318d71c2015-07-06 16:47:44 -0600912 &dev);
Simon Glassb94dc892015-03-05 12:25:25 -0700913 }
Simon Glassc45abf12015-09-08 17:52:49 -0600914 if (ret == -EPERM)
915 continue;
916 else if (ret)
Simon Glassb94dc892015-03-05 12:25:25 -0700917 return ret;
918
919 /* Update the platform data */
Simon Glass71fa5b42020-12-03 16:55:18 -0700920 pplat = dev_get_parent_plat(dev);
Simon Glassc45abf12015-09-08 17:52:49 -0600921 pplat->devfn = PCI_MASK_BUS(bdf);
922 pplat->vendor = vendor;
923 pplat->device = device;
924 pplat->class = class;
Suneel Garapatia99a5eb2019-10-23 18:40:36 -0700925
926 if (IS_ENABLED(CONFIG_PCI_ARID)) {
927 ari_off = dm_pci_find_ext_capability(dev,
928 PCI_EXT_CAP_ID_ARI);
929 if (ari_off) {
930 u16 ari_cap;
931
932 /*
933 * Read Next Function number in ARI Cap
934 * Register
935 */
936 dm_pci_read_config16(dev, ari_off + 4,
937 &ari_cap);
938 /*
939 * Update next scan on this function number,
940 * subtract 1 in BDF to satisfy loop increment.
941 */
942 if (ari_cap & 0xff00) {
943 bdf = PCI_BDF(PCI_BUS(bdf),
944 PCI_DEV(ari_cap),
945 PCI_FUNC(ari_cap));
946 bdf = bdf - 0x100;
947 }
948 }
949 }
Tim Harvey4c57bf72021-04-16 14:53:47 -0700950
951 board_pci_fixup_dev(bus, dev);
Simon Glassb94dc892015-03-05 12:25:25 -0700952 }
953
954 return 0;
Simon Glassb94dc892015-03-05 12:25:25 -0700955}
956
Christian Gmeiner5f4e0942018-06-10 06:25:05 -0700957static void decode_regions(struct pci_controller *hose, ofnode parent_node,
958 ofnode node)
Simon Glassb94dc892015-03-05 12:25:25 -0700959{
960 int pci_addr_cells, addr_cells, size_cells;
961 int cells_per_record;
Stefan Roesebbc88462020-08-12 11:55:46 +0200962 struct bd_info *bd;
Simon Glassb94dc892015-03-05 12:25:25 -0700963 const u32 *prop;
Stefan Roese950864f2020-07-23 16:34:10 +0200964 int max_regions;
Simon Glassb94dc892015-03-05 12:25:25 -0700965 int len;
966 int i;
967
Masahiro Yamada9cf85cb2017-06-22 16:54:05 +0900968 prop = ofnode_get_property(node, "ranges", &len);
Christian Gmeiner5f4e0942018-06-10 06:25:05 -0700969 if (!prop) {
970 debug("%s: Cannot decode regions\n", __func__);
971 return;
972 }
973
Simon Glass4191dc12017-06-12 06:21:31 -0600974 pci_addr_cells = ofnode_read_simple_addr_cells(node);
975 addr_cells = ofnode_read_simple_addr_cells(parent_node);
976 size_cells = ofnode_read_simple_size_cells(node);
Simon Glassb94dc892015-03-05 12:25:25 -0700977
978 /* PCI addresses are always 3-cells */
979 len /= sizeof(u32);
980 cells_per_record = pci_addr_cells + addr_cells + size_cells;
981 hose->region_count = 0;
982 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
983 cells_per_record);
Stefan Roese950864f2020-07-23 16:34:10 +0200984
985 /* Dynamically allocate the regions array */
986 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
987 hose->regions = (struct pci_region *)
988 calloc(1, max_regions * sizeof(struct pci_region));
989
990 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
Simon Glassb94dc892015-03-05 12:25:25 -0700991 u64 pci_addr, addr, size;
992 int space_code;
993 u32 flags;
994 int type;
Simon Glass7efc9ba2015-11-19 20:26:58 -0700995 int pos;
Simon Glassb94dc892015-03-05 12:25:25 -0700996
997 if (len < cells_per_record)
998 break;
999 flags = fdt32_to_cpu(prop[0]);
1000 space_code = (flags >> 24) & 3;
1001 pci_addr = fdtdec_get_number(prop + 1, 2);
1002 prop += pci_addr_cells;
1003 addr = fdtdec_get_number(prop, addr_cells);
1004 prop += addr_cells;
1005 size = fdtdec_get_number(prop, size_cells);
1006 prop += size_cells;
Masahiro Yamadac7570a32018-08-06 20:47:40 +09001007 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
1008 __func__, hose->region_count, pci_addr, addr, size, space_code);
Simon Glassb94dc892015-03-05 12:25:25 -07001009 if (space_code & 2) {
1010 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
1011 PCI_REGION_MEM;
1012 } else if (space_code & 1) {
1013 type = PCI_REGION_IO;
1014 } else {
1015 continue;
1016 }
Tuomas Tynkkynenc307e172018-05-14 18:47:50 +03001017
1018 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
1019 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
Andrew Scullcb06f0e2022-04-21 16:11:07 +00001020 debug(" - pci_addr beyond the 32-bit boundary, ignoring\n");
1021 continue;
1022 }
1023
1024 if (!IS_ENABLED(CONFIG_PHYS_64BIT) && upper_32_bits(addr)) {
1025 debug(" - addr beyond the 32-bit boundary, ignoring\n");
1026 continue;
1027 }
1028
1029 if (~((pci_addr_t)0) - pci_addr < size) {
1030 debug(" - PCI range exceeds max address, ignoring\n");
1031 continue;
1032 }
1033
1034 if (~((phys_addr_t)0) - addr < size) {
1035 debug(" - phys range exceeds max address, ignoring\n");
Tuomas Tynkkynenc307e172018-05-14 18:47:50 +03001036 continue;
1037 }
1038
Simon Glass7efc9ba2015-11-19 20:26:58 -07001039 pos = -1;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001040 if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
1041 for (i = 0; i < hose->region_count; i++) {
1042 if (hose->regions[i].flags == type)
1043 pos = i;
1044 }
Simon Glass7efc9ba2015-11-19 20:26:58 -07001045 }
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001046
Simon Glass7efc9ba2015-11-19 20:26:58 -07001047 if (pos == -1)
1048 pos = hose->region_count++;
1049 debug(" - type=%d, pos=%d\n", type, pos);
1050 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
Simon Glassb94dc892015-03-05 12:25:25 -07001051 }
1052
1053 /* Add a region for our local memory */
Stefan Roesebbc88462020-08-12 11:55:46 +02001054 bd = gd->bd;
Bin Mengae0bdde2018-03-27 00:46:05 -07001055 if (!bd)
Christian Gmeiner5f4e0942018-06-10 06:25:05 -07001056 return;
Bin Mengae0bdde2018-03-27 00:46:05 -07001057
Bernhard Messerklinger9c5df382018-02-15 08:59:53 +01001058 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
1059 if (bd->bi_dram[i].size) {
Daniel Schwierzeckf59925e2021-07-15 20:53:56 +02001060 phys_addr_t start = bd->bi_dram[i].start;
1061
1062 if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
1063 start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
1064
Bernhard Messerklinger9c5df382018-02-15 08:59:53 +01001065 pci_set_region(hose->regions + hose->region_count++,
Daniel Schwierzeckf59925e2021-07-15 20:53:56 +02001066 start, start, bd->bi_dram[i].size,
Bernhard Messerklinger9c5df382018-02-15 08:59:53 +01001067 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1068 }
1069 }
Simon Glassb94dc892015-03-05 12:25:25 -07001070
Christian Gmeiner5f4e0942018-06-10 06:25:05 -07001071 return;
Simon Glassb94dc892015-03-05 12:25:25 -07001072}
1073
1074static int pci_uclass_pre_probe(struct udevice *bus)
1075{
1076 struct pci_controller *hose;
Simon Glassbe706102020-12-16 21:20:18 -07001077 struct uclass *uc;
1078 int ret;
Simon Glassb94dc892015-03-05 12:25:25 -07001079
Simon Glass75e534b2020-12-16 21:20:07 -07001080 debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
Simon Glassb94dc892015-03-05 12:25:25 -07001081 bus->parent->name);
Simon Glass95588622020-12-22 19:30:28 -07001082 hose = dev_get_uclass_priv(bus);
Simon Glassb94dc892015-03-05 12:25:25 -07001083
Simon Glassbe706102020-12-16 21:20:18 -07001084 /*
1085 * Set the sequence number, if device_bind() doesn't. We want control
1086 * of this so that numbers are allocated as devices are probed. That
1087 * ensures that sub-bus numbered is correct (sub-buses must get numbers
1088 * higher than their parents)
1089 */
1090 if (dev_seq(bus) == -1) {
1091 ret = uclass_get(UCLASS_PCI, &uc);
1092 if (ret)
1093 return ret;
Simon Glass5e349922020-12-19 10:40:09 -07001094 bus->seq_ = uclass_find_next_free_seq(uc);
Simon Glassbe706102020-12-16 21:20:18 -07001095 }
1096
Simon Glassb94dc892015-03-05 12:25:25 -07001097 /* For bridges, use the top-level PCI controller */
Paul Burtone3b106d2016-09-08 07:47:32 +01001098 if (!device_is_on_pci_bus(bus)) {
Simon Glassb94dc892015-03-05 12:25:25 -07001099 hose->ctlr = bus;
Christian Gmeiner5f4e0942018-06-10 06:25:05 -07001100 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
Simon Glassb94dc892015-03-05 12:25:25 -07001101 } else {
1102 struct pci_controller *parent_hose;
1103
1104 parent_hose = dev_get_uclass_priv(bus->parent);
1105 hose->ctlr = parent_hose->bus;
1106 }
Simon Glassbe706102020-12-16 21:20:18 -07001107
Simon Glassb94dc892015-03-05 12:25:25 -07001108 hose->bus = bus;
Simon Glass75e534b2020-12-16 21:20:07 -07001109 hose->first_busno = dev_seq(bus);
1110 hose->last_busno = dev_seq(bus);
Simon Glassf1d50f72020-12-19 10:40:13 -07001111 if (dev_has_ofnode(bus)) {
Suneel Garapatif8c86282020-05-04 21:25:25 -07001112 hose->skip_auto_config_until_reloc =
1113 dev_read_bool(bus,
1114 "u-boot,skip-auto-config-until-reloc");
1115 }
Simon Glassb94dc892015-03-05 12:25:25 -07001116
1117 return 0;
1118}
1119
1120static int pci_uclass_post_probe(struct udevice *bus)
1121{
Simon Glass68e35a72019-12-06 21:41:37 -07001122 struct pci_controller *hose = dev_get_uclass_priv(bus);
Simon Glassb94dc892015-03-05 12:25:25 -07001123 int ret;
1124
Simon Glass75e534b2020-12-16 21:20:07 -07001125 debug("%s: probing bus %d\n", __func__, dev_seq(bus));
Simon Glassb94dc892015-03-05 12:25:25 -07001126 ret = pci_bind_bus_devices(bus);
1127 if (ret)
Simon Glassbe706102020-12-16 21:20:18 -07001128 return log_msg_ret("bind", ret);
Simon Glassb94dc892015-03-05 12:25:25 -07001129
Simon Glassbd165e72020-04-26 09:12:56 -06001130 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
Simon Glass68e35a72019-12-06 21:41:37 -07001131 (!hose->skip_auto_config_until_reloc ||
1132 (gd->flags & GD_FLG_RELOC))) {
1133 ret = pci_auto_config_devices(bus);
1134 if (ret < 0)
Simon Glassbe706102020-12-16 21:20:18 -07001135 return log_msg_ret("cfg", ret);
Simon Glass68e35a72019-12-06 21:41:37 -07001136 }
Simon Glassb94dc892015-03-05 12:25:25 -07001137
Bin Mengc0820a42015-08-20 06:40:23 -07001138#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1139 /*
1140 * Per Intel FSP specification, we should call FSP notify API to
1141 * inform FSP that PCI enumeration has been done so that FSP will
1142 * do any necessary initialization as required by the chipset's
1143 * BIOS Writer's Guide (BWG).
1144 *
1145 * Unfortunately we have to put this call here as with driver model,
1146 * the enumeration is all done on a lazy basis as needed, so until
1147 * something is touched on PCI it won't happen.
1148 *
1149 * Note we only call this 1) after U-Boot is relocated, and 2)
1150 * root bus has finished probing.
1151 */
Simon Glass75e534b2020-12-16 21:20:07 -07001152 if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
Bin Mengc0820a42015-08-20 06:40:23 -07001153 ret = fsp_init_phase_pci();
Simon Glassb072d522015-09-08 17:52:47 -06001154 if (ret)
Simon Glassbe706102020-12-16 21:20:18 -07001155 return log_msg_ret("fsp", ret);
Simon Glassb072d522015-09-08 17:52:47 -06001156 }
Bin Mengc0820a42015-08-20 06:40:23 -07001157#endif
1158
Simon Glassb072d522015-09-08 17:52:47 -06001159 return 0;
Simon Glassb94dc892015-03-05 12:25:25 -07001160}
1161
1162static int pci_uclass_child_post_bind(struct udevice *dev)
1163{
Simon Glassb75b15b2020-12-03 16:55:23 -07001164 struct pci_child_plat *pplat;
Simon Glassb94dc892015-03-05 12:25:25 -07001165
Simon Glassf1d50f72020-12-19 10:40:13 -07001166 if (!dev_has_ofnode(dev))
Simon Glassb94dc892015-03-05 12:25:25 -07001167 return 0;
1168
Simon Glass71fa5b42020-12-03 16:55:18 -07001169 pplat = dev_get_parent_plat(dev);
Bin Meng00d808e2018-08-03 01:14:36 -07001170
1171 /* Extract vendor id and device id if available */
1172 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1173
1174 /* Extract the devfn from fdt_pci_addr */
Stefan Roesea74eb552019-01-25 11:52:42 +01001175 pplat->devfn = pci_get_devfn(dev);
Simon Glassb94dc892015-03-05 12:25:25 -07001176
1177 return 0;
1178}
1179
Simon Glass2a311e82020-01-27 08:49:37 -07001180static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
Bin Meng0a721522015-07-19 00:20:04 +08001181 uint offset, ulong *valuep,
1182 enum pci_size_t size)
Simon Glassb94dc892015-03-05 12:25:25 -07001183{
Simon Glass95588622020-12-22 19:30:28 -07001184 struct pci_controller *hose = dev_get_uclass_priv(bus);
Simon Glassb94dc892015-03-05 12:25:25 -07001185
1186 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1187}
1188
Bin Meng0a721522015-07-19 00:20:04 +08001189static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1190 uint offset, ulong value,
1191 enum pci_size_t size)
Simon Glassb94dc892015-03-05 12:25:25 -07001192{
Simon Glass95588622020-12-22 19:30:28 -07001193 struct pci_controller *hose = dev_get_uclass_priv(bus);
Simon Glassb94dc892015-03-05 12:25:25 -07001194
1195 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1196}
1197
Simon Glass04c8b6a2015-08-10 07:05:04 -06001198static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1199{
1200 struct udevice *dev;
1201 int ret = 0;
1202
1203 /*
1204 * Scan through all the PCI controllers. On x86 there will only be one
1205 * but that is not necessarily true on other hardware.
1206 */
1207 do {
1208 device_find_first_child(bus, &dev);
1209 if (dev) {
1210 *devp = dev;
1211 return 0;
1212 }
1213 ret = uclass_next_device(&bus);
1214 if (ret)
1215 return ret;
1216 } while (bus);
1217
1218 return 0;
1219}
1220
1221int pci_find_next_device(struct udevice **devp)
1222{
1223 struct udevice *child = *devp;
1224 struct udevice *bus = child->parent;
1225 int ret;
1226
1227 /* First try all the siblings */
1228 *devp = NULL;
1229 while (child) {
1230 device_find_next_child(&child);
1231 if (child) {
1232 *devp = child;
1233 return 0;
1234 }
1235 }
1236
1237 /* We ran out of siblings. Try the next bus */
1238 ret = uclass_next_device(&bus);
1239 if (ret)
1240 return ret;
1241
1242 return bus ? skip_to_next_device(bus, devp) : 0;
1243}
1244
1245int pci_find_first_device(struct udevice **devp)
1246{
1247 struct udevice *bus;
1248 int ret;
1249
1250 *devp = NULL;
1251 ret = uclass_first_device(UCLASS_PCI, &bus);
1252 if (ret)
1253 return ret;
1254
1255 return skip_to_next_device(bus, devp);
1256}
1257
Simon Glass27a733f2015-11-19 20:26:59 -07001258ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1259{
1260 switch (size) {
1261 case PCI_SIZE_8:
1262 return (value >> ((offset & 3) * 8)) & 0xff;
1263 case PCI_SIZE_16:
1264 return (value >> ((offset & 2) * 8)) & 0xffff;
1265 default:
1266 return value;
1267 }
1268}
1269
1270ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1271 enum pci_size_t size)
1272{
1273 uint off_mask;
1274 uint val_mask, shift;
1275 ulong ldata, mask;
1276
1277 switch (size) {
1278 case PCI_SIZE_8:
1279 off_mask = 3;
1280 val_mask = 0xff;
1281 break;
1282 case PCI_SIZE_16:
1283 off_mask = 2;
1284 val_mask = 0xffff;
1285 break;
1286 default:
1287 return value;
1288 }
1289 shift = (offset & off_mask) * 8;
1290 ldata = (value & val_mask) << shift;
1291 mask = val_mask << shift;
1292 value = (old & ~mask) | ldata;
1293
1294 return value;
1295}
1296
Rayagonda Kokatanurcdc7ed32020-05-12 13:29:49 +05301297int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1298{
1299 int pci_addr_cells, addr_cells, size_cells;
1300 int cells_per_record;
1301 const u32 *prop;
1302 int len;
1303 int i = 0;
1304
1305 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1306 if (!prop) {
1307 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1308 dev->name);
1309 return -EINVAL;
1310 }
1311
1312 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1313 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1314 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1315
1316 /* PCI addresses are always 3-cells */
1317 len /= sizeof(u32);
1318 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1319 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1320 cells_per_record);
1321
1322 while (len) {
1323 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1324 prop += pci_addr_cells;
1325 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1326 prop += addr_cells;
1327 memp->size = fdtdec_get_number(prop, size_cells);
1328 prop += size_cells;
1329
1330 if (i == index)
1331 return 0;
1332 i++;
1333 len -= cells_per_record;
1334 }
1335
1336 return -EINVAL;
1337}
1338
Simon Glassdcdc0122015-11-19 20:27:01 -07001339int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1340 struct pci_region **memp, struct pci_region **prefp)
1341{
1342 struct udevice *bus = pci_get_controller(dev);
1343 struct pci_controller *hose = dev_get_uclass_priv(bus);
1344 int i;
1345
1346 *iop = NULL;
1347 *memp = NULL;
1348 *prefp = NULL;
1349 for (i = 0; i < hose->region_count; i++) {
1350 switch (hose->regions[i].flags) {
1351 case PCI_REGION_IO:
1352 if (!*iop || (*iop)->size < hose->regions[i].size)
1353 *iop = hose->regions + i;
1354 break;
1355 case PCI_REGION_MEM:
1356 if (!*memp || (*memp)->size < hose->regions[i].size)
1357 *memp = hose->regions + i;
1358 break;
1359 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1360 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1361 *prefp = hose->regions + i;
1362 break;
1363 }
1364 }
1365
1366 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1367}
1368
Simon Glassc92aac12020-01-27 08:49:38 -07001369u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
Simon Glass3452cb12015-11-29 13:17:53 -07001370{
1371 u32 addr;
1372 int bar;
1373
1374 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1375 dm_pci_read_config32(dev, bar, &addr);
Simon Glass71fafd12020-04-09 10:27:36 -06001376
1377 /*
1378 * If we get an invalid address, return this so that comparisons with
1379 * FDT_ADDR_T_NONE work correctly
1380 */
1381 if (addr == 0xffffffff)
1382 return addr;
1383 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
Simon Glass3452cb12015-11-29 13:17:53 -07001384 return addr & PCI_BASE_ADDRESS_IO_MASK;
1385 else
1386 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1387}
1388
Simon Glasse2b6b562016-01-18 20:19:15 -07001389void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1390{
1391 int bar;
1392
1393 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1394 dm_pci_write_config32(dev, bar, addr);
1395}
1396
Andrew Scull994b60d2022-04-21 16:11:11 +00001397phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1398 size_t len, unsigned long mask,
1399 unsigned long flags)
Simon Glassc5f053b2015-11-29 13:18:03 -07001400{
Andrew Scull994b60d2022-04-21 16:11:11 +00001401 struct udevice *ctlr;
1402 struct pci_controller *hose;
Simon Glassc5f053b2015-11-29 13:18:03 -07001403 struct pci_region *res;
Andrew Scull3bf61522022-04-21 16:11:08 +00001404 pci_addr_t offset;
Simon Glassc5f053b2015-11-29 13:18:03 -07001405 int i;
1406
Andrew Scull994b60d2022-04-21 16:11:11 +00001407 /* The root controller has the region information */
1408 ctlr = pci_get_controller(dev);
1409 hose = dev_get_uclass_priv(ctlr);
1410
1411 if (hose->region_count == 0)
1412 return bus_addr;
Christian Gmeiner7241f802018-06-10 06:25:06 -07001413
Simon Glassc5f053b2015-11-29 13:18:03 -07001414 for (i = 0; i < hose->region_count; i++) {
1415 res = &hose->regions[i];
1416
Andrew Scull994b60d2022-04-21 16:11:11 +00001417 if ((res->flags & mask) != flags)
Simon Glassc5f053b2015-11-29 13:18:03 -07001418 continue;
1419
Andrew Scull3bf61522022-04-21 16:11:08 +00001420 if (bus_addr < res->bus_start)
1421 continue;
1422
1423 offset = bus_addr - res->bus_start;
1424 if (offset >= res->size)
1425 continue;
1426
1427 if (len > res->size - offset)
1428 continue;
1429
Andrew Scull994b60d2022-04-21 16:11:11 +00001430 return res->phys_start + offset;
Simon Glassc5f053b2015-11-29 13:18:03 -07001431 }
1432
Andrew Scull994b60d2022-04-21 16:11:11 +00001433 puts("pci_hose_bus_to_phys: invalid physical address\n");
1434 return 0;
Simon Glassc5f053b2015-11-29 13:18:03 -07001435}
1436
Andrew Scull994b60d2022-04-21 16:11:11 +00001437pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1438 size_t len, unsigned long mask,
1439 unsigned long flags)
Simon Glassc5f053b2015-11-29 13:18:03 -07001440{
Simon Glassc5f053b2015-11-29 13:18:03 -07001441 struct udevice *ctlr;
Andrew Scull994b60d2022-04-21 16:11:11 +00001442 struct pci_controller *hose;
Simon Glassc5f053b2015-11-29 13:18:03 -07001443 struct pci_region *res;
Andrew Scull3bf61522022-04-21 16:11:08 +00001444 phys_addr_t offset;
Simon Glassc5f053b2015-11-29 13:18:03 -07001445 int i;
Simon Glassc5f053b2015-11-29 13:18:03 -07001446
1447 /* The root controller has the region information */
1448 ctlr = pci_get_controller(dev);
1449 hose = dev_get_uclass_priv(ctlr);
1450
Andrew Scull994b60d2022-04-21 16:11:11 +00001451 if (hose->region_count == 0)
1452 return phys_addr;
Christian Gmeiner7241f802018-06-10 06:25:06 -07001453
Simon Glassc5f053b2015-11-29 13:18:03 -07001454 for (i = 0; i < hose->region_count; i++) {
1455 res = &hose->regions[i];
1456
Andrew Scull994b60d2022-04-21 16:11:11 +00001457 if ((res->flags & mask) != flags)
Simon Glassc5f053b2015-11-29 13:18:03 -07001458 continue;
1459
Andrew Scull3bf61522022-04-21 16:11:08 +00001460 if (phys_addr < res->phys_start)
1461 continue;
1462
1463 offset = phys_addr - res->phys_start;
1464 if (offset >= res->size)
1465 continue;
Simon Glassc5f053b2015-11-29 13:18:03 -07001466
Andrew Scull3bf61522022-04-21 16:11:08 +00001467 if (len > res->size - offset)
1468 continue;
1469
Andrew Scull994b60d2022-04-21 16:11:11 +00001470 return res->bus_start + offset;
Simon Glassc5f053b2015-11-29 13:18:03 -07001471 }
1472
Andrew Scull994b60d2022-04-21 16:11:11 +00001473 puts("pci_hose_phys_to_bus: invalid physical address\n");
1474 return 0;
Simon Glassc5f053b2015-11-29 13:18:03 -07001475}
1476
Suneel Garapati5858ba82019-10-19 16:34:16 -07001477static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
Simon Glassb75b15b2020-12-03 16:55:23 -07001478 struct pci_child_plat *pdata)
Suneel Garapati5858ba82019-10-19 16:34:16 -07001479{
1480 phys_addr_t addr = 0;
1481
1482 /*
1483 * In the case of a Virtual Function device using BAR
1484 * base and size, add offset for VFn BAR(1, 2, 3...n)
1485 */
1486 if (pdata->is_virtfn) {
1487 size_t sz;
1488 u32 ea_entry;
1489
1490 /* MaxOffset, 1st DW */
1491 dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
1492 sz = ea_entry & PCI_EA_FIELD_MASK;
1493 /* Fill up lower 2 bits */
1494 sz |= (~PCI_EA_FIELD_MASK);
1495
1496 if (ea_entry & PCI_EA_IS_64) {
1497 /* MaxOffset 2nd DW */
1498 dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
1499 sz |= ((u64)ea_entry) << 32;
1500 }
1501
1502 addr = (pdata->virtid - 1) * (sz + 1);
1503 }
1504
1505 return addr;
1506}
1507
Andrew Scull58c61022022-04-21 16:11:10 +00001508static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, size_t offset,
1509 size_t len, int ea_off,
Andrew Scull30d338d2022-04-21 16:11:06 +00001510 struct pci_child_plat *pdata)
Alex Marginean1c934a62019-06-07 11:24:23 +03001511{
1512 int ea_cnt, i, entry_size;
1513 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1514 u32 ea_entry;
1515 phys_addr_t addr;
1516
Suneel Garapati5858ba82019-10-19 16:34:16 -07001517 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1518 /*
1519 * In the case of a Virtual Function device, device is
1520 * Physical function, so pdata will point to required VF
1521 * specific data.
1522 */
1523 if (pdata->is_virtfn)
1524 bar_id += PCI_EA_BEI_VF_BAR0;
1525 }
1526
Alex Marginean1c934a62019-06-07 11:24:23 +03001527 /* EA capability structure header */
1528 dm_pci_read_config32(dev, ea_off, &ea_entry);
1529 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1530 ea_off += PCI_EA_FIRST_ENT;
1531
1532 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1533 /* Entry header */
1534 dm_pci_read_config32(dev, ea_off, &ea_entry);
1535 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1536
1537 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1538 continue;
1539
1540 /* Base address, 1st DW */
1541 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1542 addr = ea_entry & PCI_EA_FIELD_MASK;
1543 if (ea_entry & PCI_EA_IS_64) {
1544 /* Base address, 2nd DW, skip over 4B MaxOffset */
1545 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1546 addr |= ((u64)ea_entry) << 32;
1547 }
1548
Suneel Garapati5858ba82019-10-19 16:34:16 -07001549 if (IS_ENABLED(CONFIG_PCI_SRIOV))
1550 addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
1551
Andrew Scull58c61022022-04-21 16:11:10 +00001552 if (~((phys_addr_t)0) - addr < offset)
1553 return NULL;
1554
Alex Marginean1c934a62019-06-07 11:24:23 +03001555 /* size ignored for now */
Andrew Scull58c61022022-04-21 16:11:10 +00001556 return map_physmem(addr + offset, len, MAP_NOCACHE);
Alex Marginean1c934a62019-06-07 11:24:23 +03001557 }
1558
1559 return 0;
1560}
1561
Andrew Scull58c61022022-04-21 16:11:10 +00001562void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len,
Andrew Scull6520c822022-04-21 16:11:13 +00001563 unsigned long mask, unsigned long flags)
Simon Glassc5f053b2015-11-29 13:18:03 -07001564{
Simon Glassb75b15b2020-12-03 16:55:23 -07001565 struct pci_child_plat *pdata = dev_get_parent_plat(dev);
Suneel Garapati5858ba82019-10-19 16:34:16 -07001566 struct udevice *udev = dev;
Simon Glassc5f053b2015-11-29 13:18:03 -07001567 pci_addr_t pci_bus_addr;
1568 u32 bar_response;
Alex Marginean1c934a62019-06-07 11:24:23 +03001569 int ea_off;
1570
Suneel Garapati5858ba82019-10-19 16:34:16 -07001571 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1572 /*
1573 * In case of Virtual Function devices, use PF udevice
1574 * as EA capability is defined in Physical Function
1575 */
1576 if (pdata->is_virtfn)
1577 udev = pdata->pfdev;
1578 }
1579
Alex Marginean1c934a62019-06-07 11:24:23 +03001580 /*
1581 * if the function supports Enhanced Allocation use that instead of
1582 * BARs
Suneel Garapati5858ba82019-10-19 16:34:16 -07001583 * Incase of virtual functions, pdata will help read VF BEI
1584 * and EA entry size.
Alex Marginean1c934a62019-06-07 11:24:23 +03001585 */
Andrew Scull71e7e1a2022-04-21 16:11:16 +00001586 if (IS_ENABLED(CONFIG_PCI_ENHANCED_ALLOCATION))
1587 ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
1588 else
1589 ea_off = 0;
1590
Alex Marginean1c934a62019-06-07 11:24:23 +03001591 if (ea_off)
Andrew Scull58c61022022-04-21 16:11:10 +00001592 return dm_pci_map_ea_bar(udev, bar, offset, len, ea_off, pdata);
Simon Glassc5f053b2015-11-29 13:18:03 -07001593
1594 /* read BAR address */
Suneel Garapati5858ba82019-10-19 16:34:16 -07001595 dm_pci_read_config32(udev, bar, &bar_response);
Simon Glassc5f053b2015-11-29 13:18:03 -07001596 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1597
Andrew Scull58c61022022-04-21 16:11:10 +00001598 if (~((pci_addr_t)0) - pci_bus_addr < offset)
1599 return NULL;
1600
Simon Glassc5f053b2015-11-29 13:18:03 -07001601 /*
Andrew Scull58c61022022-04-21 16:11:10 +00001602 * Forward the length argument to dm_pci_bus_to_virt. The length will
1603 * be used to check that the entire address range has been declared as
1604 * a PCI range, but a better check would be to probe for the size of
1605 * the bar and prevent overflow more locally.
Simon Glassc5f053b2015-11-29 13:18:03 -07001606 */
Andrew Scull6520c822022-04-21 16:11:13 +00001607 return dm_pci_bus_to_virt(udev, pci_bus_addr + offset, len, mask, flags,
1608 MAP_NOCACHE);
Simon Glassc5f053b2015-11-29 13:18:03 -07001609}
1610
Bin Meng631f3482018-10-15 02:21:21 -07001611static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
Bin Menga7366f02018-08-03 01:14:52 -07001612{
Bin Menga7366f02018-08-03 01:14:52 -07001613 int ttl = PCI_FIND_CAP_TTL;
1614 u8 id;
1615 u16 ent;
Bin Menga7366f02018-08-03 01:14:52 -07001616
1617 dm_pci_read_config8(dev, pos, &pos);
Bin Meng631f3482018-10-15 02:21:21 -07001618
Bin Menga7366f02018-08-03 01:14:52 -07001619 while (ttl--) {
1620 if (pos < PCI_STD_HEADER_SIZEOF)
1621 break;
1622 pos &= ~3;
1623 dm_pci_read_config16(dev, pos, &ent);
1624
1625 id = ent & 0xff;
1626 if (id == 0xff)
1627 break;
1628 if (id == cap)
1629 return pos;
1630 pos = (ent >> 8);
1631 }
1632
1633 return 0;
1634}
1635
Bin Meng631f3482018-10-15 02:21:21 -07001636int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1637{
1638 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1639 cap);
1640}
1641
1642int dm_pci_find_capability(struct udevice *dev, int cap)
1643{
1644 u16 status;
1645 u8 header_type;
1646 u8 pos;
1647
1648 dm_pci_read_config16(dev, PCI_STATUS, &status);
1649 if (!(status & PCI_STATUS_CAP_LIST))
1650 return 0;
1651
1652 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1653 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1654 pos = PCI_CB_CAPABILITY_LIST;
1655 else
1656 pos = PCI_CAPABILITY_LIST;
1657
1658 return _dm_pci_find_next_capability(dev, pos, cap);
1659}
1660
1661int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
Bin Menga7366f02018-08-03 01:14:52 -07001662{
1663 u32 header;
1664 int ttl;
1665 int pos = PCI_CFG_SPACE_SIZE;
1666
1667 /* minimum 8 bytes per capability */
1668 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1669
Bin Meng631f3482018-10-15 02:21:21 -07001670 if (start)
1671 pos = start;
1672
Bin Menga7366f02018-08-03 01:14:52 -07001673 dm_pci_read_config32(dev, pos, &header);
1674 /*
1675 * If we have no capabilities, this is indicated by cap ID,
1676 * cap version and next pointer all being 0.
1677 */
1678 if (header == 0)
1679 return 0;
1680
1681 while (ttl--) {
1682 if (PCI_EXT_CAP_ID(header) == cap)
1683 return pos;
1684
1685 pos = PCI_EXT_CAP_NEXT(header);
1686 if (pos < PCI_CFG_SPACE_SIZE)
1687 break;
1688
1689 dm_pci_read_config32(dev, pos, &header);
1690 }
1691
1692 return 0;
1693}
1694
Bin Meng631f3482018-10-15 02:21:21 -07001695int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1696{
1697 return dm_pci_find_next_ext_capability(dev, 0, cap);
1698}
1699
Alex Marginean09467d32019-06-07 11:24:25 +03001700int dm_pci_flr(struct udevice *dev)
1701{
1702 int pcie_off;
1703 u32 cap;
1704
1705 /* look for PCI Express Capability */
1706 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1707 if (!pcie_off)
1708 return -ENOENT;
1709
1710 /* check FLR capability */
1711 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1712 if (!(cap & PCI_EXP_DEVCAP_FLR))
1713 return -ENOENT;
1714
1715 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1716 PCI_EXP_DEVCTL_BCR_FLR);
1717
1718 /* wait 100ms, per PCI spec */
1719 mdelay(100);
1720
1721 return 0;
1722}
1723
Suneel Garapati13822f72019-10-19 16:07:20 -07001724#if defined(CONFIG_PCI_SRIOV)
1725int pci_sriov_init(struct udevice *pdev, int vf_en)
1726{
1727 u16 vendor, device;
1728 struct udevice *bus;
1729 struct udevice *dev;
1730 pci_dev_t bdf;
1731 u16 ctrl;
1732 u16 num_vfs;
1733 u16 total_vf;
1734 u16 vf_offset;
1735 u16 vf_stride;
1736 int vf, ret;
1737 int pos;
1738
1739 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1740 if (!pos) {
1741 debug("Error: SRIOV capability not found\n");
1742 return -ENOENT;
1743 }
1744
1745 dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
1746
1747 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1748 if (vf_en > total_vf)
1749 vf_en = total_vf;
1750 dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
1751
1752 ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
1753 dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
1754
1755 dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
1756 if (num_vfs > vf_en)
1757 num_vfs = vf_en;
1758
1759 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
1760 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
1761
1762 dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
1763 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
1764
1765 bdf = dm_pci_get_bdf(pdev);
1766
1767 pci_get_bus(PCI_BUS(bdf), &bus);
1768
1769 if (!bus)
1770 return -ENODEV;
1771
1772 bdf += PCI_BDF(0, 0, vf_offset);
1773
1774 for (vf = 0; vf < num_vfs; vf++) {
Simon Glassb75b15b2020-12-03 16:55:23 -07001775 struct pci_child_plat *pplat;
Suneel Garapati13822f72019-10-19 16:07:20 -07001776 ulong class;
1777
1778 pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
1779 &class, PCI_SIZE_16);
1780
1781 debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
Simon Glass75e534b2020-12-16 21:20:07 -07001782 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
Suneel Garapati13822f72019-10-19 16:07:20 -07001783
1784 /* Find this device in the device tree */
1785 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
1786
1787 if (ret == -ENODEV) {
1788 struct pci_device_id find_id;
1789
1790 memset(&find_id, '\0', sizeof(find_id));
1791 find_id.vendor = vendor;
1792 find_id.device = device;
1793 find_id.class = class;
1794
1795 ret = pci_find_and_bind_driver(bus, &find_id,
1796 bdf, &dev);
1797
1798 if (ret)
1799 return ret;
1800 }
1801
1802 /* Update the platform data */
Simon Glass71fa5b42020-12-03 16:55:18 -07001803 pplat = dev_get_parent_plat(dev);
Suneel Garapati13822f72019-10-19 16:07:20 -07001804 pplat->devfn = PCI_MASK_BUS(bdf);
1805 pplat->vendor = vendor;
1806 pplat->device = device;
1807 pplat->class = class;
1808 pplat->is_virtfn = true;
1809 pplat->pfdev = pdev;
1810 pplat->virtid = vf * vf_stride + vf_offset;
1811
1812 debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
Simon Glass75e534b2020-12-16 21:20:07 -07001813 __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
Suneel Garapati13822f72019-10-19 16:07:20 -07001814 PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
1815 bdf += PCI_BDF(0, 0, vf_stride);
1816 }
1817
1818 return 0;
1819}
1820
1821int pci_sriov_get_totalvfs(struct udevice *pdev)
1822{
1823 u16 total_vf;
1824 int pos;
1825
1826 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1827 if (!pos) {
1828 debug("Error: SRIOV capability not found\n");
1829 return -ENOENT;
1830 }
1831
1832 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1833
1834 return total_vf;
1835}
1836#endif /* SRIOV */
1837
Simon Glassb94dc892015-03-05 12:25:25 -07001838UCLASS_DRIVER(pci) = {
1839 .id = UCLASS_PCI,
1840 .name = "pci",
Simon Glassbe706102020-12-16 21:20:18 -07001841 .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
Simon Glass18230342016-07-05 17:10:10 -06001842 .post_bind = dm_scan_fdt_dev,
Simon Glassb94dc892015-03-05 12:25:25 -07001843 .pre_probe = pci_uclass_pre_probe,
1844 .post_probe = pci_uclass_post_probe,
1845 .child_post_bind = pci_uclass_child_post_bind,
Simon Glass8a2b47f2020-12-03 16:55:17 -07001846 .per_device_auto = sizeof(struct pci_controller),
Simon Glassb75b15b2020-12-03 16:55:23 -07001847 .per_child_plat_auto = sizeof(struct pci_child_plat),
Simon Glassb94dc892015-03-05 12:25:25 -07001848};
1849
1850static const struct dm_pci_ops pci_bridge_ops = {
1851 .read_config = pci_bridge_read_config,
1852 .write_config = pci_bridge_write_config,
1853};
1854
1855static const struct udevice_id pci_bridge_ids[] = {
1856 { .compatible = "pci-bridge" },
1857 { }
1858};
1859
1860U_BOOT_DRIVER(pci_bridge_drv) = {
1861 .name = "pci_bridge_drv",
1862 .id = UCLASS_PCI,
1863 .of_match = pci_bridge_ids,
1864 .ops = &pci_bridge_ops,
1865};
1866
1867UCLASS_DRIVER(pci_generic) = {
1868 .id = UCLASS_PCI_GENERIC,
1869 .name = "pci_generic",
1870};
1871
1872static const struct udevice_id pci_generic_ids[] = {
1873 { .compatible = "pci-generic" },
1874 { }
1875};
1876
1877U_BOOT_DRIVER(pci_generic_drv) = {
1878 .name = "pci_generic_drv",
1879 .id = UCLASS_PCI_GENERIC,
1880 .of_match = pci_generic_ids,
1881};
Stephen Warren04eb2692016-01-26 11:10:11 -07001882
Ovidiu Panaite353edb2020-11-28 10:43:12 +02001883int pci_init(void)
Stephen Warren04eb2692016-01-26 11:10:11 -07001884{
1885 struct udevice *bus;
1886
1887 /*
1888 * Enumerate all known controller devices. Enumeration has the side-
1889 * effect of probing them, so PCIe devices will be enumerated too.
1890 */
Marek BehĂșn5df208d2019-05-21 12:04:31 +02001891 for (uclass_first_device_check(UCLASS_PCI, &bus);
Stephen Warren04eb2692016-01-26 11:10:11 -07001892 bus;
Marek BehĂșn5df208d2019-05-21 12:04:31 +02001893 uclass_next_device_check(&bus)) {
Stephen Warren04eb2692016-01-26 11:10:11 -07001894 ;
1895 }
Ovidiu Panaite353edb2020-11-28 10:43:12 +02001896
1897 return 0;
Stephen Warren04eb2692016-01-26 11:10:11 -07001898}