Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Gabor Juhos | 02c754a | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 4 | * Copyright (C) 2013 Imagination Technologies |
Gabor Juhos | 02c754a | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Daniel Schwierzeck | 09d32c0 | 2021-07-15 20:54:00 +0200 | [diff] [blame] | 7 | #include <config.h> |
| 8 | #include <fdt_support.h> |
Paul Burton | c6c3853 | 2015-01-29 10:38:20 +0000 | [diff] [blame] | 9 | #include <ide.h> |
Simon Glass | 18afe10 | 2019-11-14 12:57:47 -0700 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 11 | #include <net.h> |
Gabor Juhos | 439c50c | 2013-05-22 03:57:44 +0000 | [diff] [blame] | 12 | #include <netdev.h> |
Paul Burton | 12ab4ab | 2013-11-08 11:18:57 +0000 | [diff] [blame] | 13 | #include <pci.h> |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 14 | #include <pci_gt64120.h> |
| 15 | #include <pci_msc01.h> |
Paul Burton | c028f9b | 2013-11-08 11:18:55 +0000 | [diff] [blame] | 16 | #include <rtc.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 17 | #include <asm/global_data.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 18 | #include <linux/delay.h> |
Gabor Juhos | 02c754a | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 19 | |
Gabor Juhos | 652ccee | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 20 | #include <asm/addrspace.h> |
Gabor Juhos | aed4fa4 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 21 | #include <asm/io.h> |
| 22 | #include <asm/malta.h> |
| 23 | |
Paul Burton | 7fb0507 | 2013-11-08 11:18:49 +0000 | [diff] [blame] | 24 | #include "superio.h" |
| 25 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
Daniel Schwierzeck | 09d32c0 | 2021-07-15 20:54:00 +0200 | [diff] [blame] | 28 | #define MALTA_GT_PATH "/pci0@1be00000" |
| 29 | #define MALTA_MSC_PATH "/pci0@1bd00000" |
| 30 | |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 31 | enum core_card { |
| 32 | CORE_UNKNOWN, |
| 33 | CORE_LV, |
| 34 | CORE_FPGA6, |
| 35 | }; |
| 36 | |
| 37 | enum sys_con { |
| 38 | SYSCON_UNKNOWN, |
| 39 | SYSCON_GT64120, |
| 40 | SYSCON_MSC01, |
| 41 | }; |
| 42 | |
Paul Burton | 7c8835b | 2013-11-08 11:18:51 +0000 | [diff] [blame] | 43 | static void malta_lcd_puts(const char *str) |
| 44 | { |
| 45 | int i; |
| 46 | void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); |
| 47 | |
| 48 | /* print up to 8 characters of the string */ |
Masahiro Yamada | db20464 | 2014-11-07 03:03:31 +0900 | [diff] [blame] | 49 | for (i = 0; i < min((int)strlen(str), 8); i++) { |
Paul Burton | 7c8835b | 2013-11-08 11:18:51 +0000 | [diff] [blame] | 50 | __raw_writel(str[i], reg); |
| 51 | reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; |
| 52 | } |
| 53 | |
| 54 | /* fill the rest of the display with spaces */ |
| 55 | for (; i < 8; i++) { |
| 56 | __raw_writel(' ', reg); |
| 57 | reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; |
| 58 | } |
| 59 | } |
| 60 | |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 61 | static enum core_card malta_core_card(void) |
| 62 | { |
| 63 | u32 corid, rev; |
Daniel Schwierzeck | 36eb053 | 2016-01-09 17:32:45 +0100 | [diff] [blame] | 64 | const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 65 | |
Daniel Schwierzeck | 36eb053 | 2016-01-09 17:32:45 +0100 | [diff] [blame] | 66 | rev = __raw_readl(reg); |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 67 | corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; |
| 68 | |
| 69 | switch (corid) { |
| 70 | case MALTA_REVISION_CORID_CORE_LV: |
| 71 | return CORE_LV; |
| 72 | |
| 73 | case MALTA_REVISION_CORID_CORE_FPGA6: |
| 74 | return CORE_FPGA6; |
| 75 | |
| 76 | default: |
| 77 | return CORE_UNKNOWN; |
| 78 | } |
| 79 | } |
| 80 | |
| 81 | static enum sys_con malta_sys_con(void) |
| 82 | { |
| 83 | switch (malta_core_card()) { |
| 84 | case CORE_LV: |
| 85 | return SYSCON_GT64120; |
| 86 | |
| 87 | case CORE_FPGA6: |
| 88 | return SYSCON_MSC01; |
| 89 | |
| 90 | default: |
| 91 | return SYSCON_UNKNOWN; |
| 92 | } |
| 93 | } |
| 94 | |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 95 | int dram_init(void) |
Gabor Juhos | 02c754a | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 96 | { |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 97 | gd->ram_size = CONFIG_SYS_MEM_SIZE; |
| 98 | |
| 99 | return 0; |
Gabor Juhos | 02c754a | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | int checkboard(void) |
| 103 | { |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 104 | enum core_card core; |
| 105 | |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 106 | malta_lcd_puts("U-Boot"); |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 107 | puts("Board: MIPS Malta"); |
| 108 | |
| 109 | core = malta_core_card(); |
| 110 | switch (core) { |
| 111 | case CORE_LV: |
| 112 | puts(" CoreLV"); |
| 113 | break; |
| 114 | |
| 115 | case CORE_FPGA6: |
| 116 | puts(" CoreFPGA6"); |
| 117 | break; |
| 118 | |
| 119 | default: |
| 120 | puts(" CoreUnknown"); |
| 121 | } |
| 122 | |
| 123 | putc('\n'); |
Gabor Juhos | 02c754a | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 124 | return 0; |
| 125 | } |
Gabor Juhos | aed4fa4 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 126 | |
Daniel Schwierzeck | 09d32c0 | 2021-07-15 20:54:00 +0200 | [diff] [blame] | 127 | #if !IS_ENABLED(CONFIG_DM_ETH) |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 128 | int board_eth_init(struct bd_info *bis) |
Gabor Juhos | 439c50c | 2013-05-22 03:57:44 +0000 | [diff] [blame] | 129 | { |
| 130 | return pci_eth_init(bis); |
| 131 | } |
Daniel Schwierzeck | 09d32c0 | 2021-07-15 20:54:00 +0200 | [diff] [blame] | 132 | #endif |
Gabor Juhos | 439c50c | 2013-05-22 03:57:44 +0000 | [diff] [blame] | 133 | |
Gabor Juhos | aed4fa4 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 134 | void _machine_restart(void) |
| 135 | { |
| 136 | void __iomem *reset_base; |
| 137 | |
| 138 | reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); |
| 139 | __raw_writel(GORESET, reset_base); |
Paul Burton | ee6af87 | 2015-01-29 10:38:21 +0000 | [diff] [blame] | 140 | mdelay(1000); |
Gabor Juhos | aed4fa4 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 141 | } |
Gabor Juhos | 652ccee | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 142 | |
Paul Burton | 7fb0507 | 2013-11-08 11:18:49 +0000 | [diff] [blame] | 143 | int board_early_init_f(void) |
| 144 | { |
Paul Burton | dd37a14 | 2016-01-29 13:54:54 +0000 | [diff] [blame] | 145 | ulong io_base; |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 146 | |
| 147 | /* choose correct PCI I/O base */ |
| 148 | switch (malta_sys_con()) { |
| 149 | case SYSCON_GT64120: |
Paul Burton | dd37a14 | 2016-01-29 13:54:54 +0000 | [diff] [blame] | 150 | io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE); |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 151 | break; |
| 152 | |
| 153 | case SYSCON_MSC01: |
Paul Burton | dd37a14 | 2016-01-29 13:54:54 +0000 | [diff] [blame] | 154 | io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); |
Paul Burton | 234882c | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 155 | break; |
| 156 | |
| 157 | default: |
| 158 | return -1; |
| 159 | } |
| 160 | |
Paul Burton | dd37a14 | 2016-01-29 13:54:54 +0000 | [diff] [blame] | 161 | set_io_port_base(io_base); |
Paul Burton | 2e9b2a9 | 2016-01-29 13:54:53 +0000 | [diff] [blame] | 162 | |
Paul Burton | 7fb0507 | 2013-11-08 11:18:49 +0000 | [diff] [blame] | 163 | /* setup FDC37M817 super I/O controller */ |
Paul Burton | dd37a14 | 2016-01-29 13:54:54 +0000 | [diff] [blame] | 164 | malta_superio_init(); |
Paul Burton | 7fb0507 | 2013-11-08 11:18:49 +0000 | [diff] [blame] | 165 | |
| 166 | return 0; |
| 167 | } |
| 168 | |
Paul Burton | c028f9b | 2013-11-08 11:18:55 +0000 | [diff] [blame] | 169 | int misc_init_r(void) |
| 170 | { |
| 171 | rtc_reset(); |
| 172 | |
| 173 | return 0; |
| 174 | } |
| 175 | |
Daniel Schwierzeck | 09d32c0 | 2021-07-15 20:54:00 +0200 | [diff] [blame] | 176 | #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) |
| 177 | /* |
| 178 | * TODO: currently doesn't work because rw_fdt_blob points to a |
| 179 | * NOR flash address. This needs some changes in board_init_f. |
| 180 | */ |
| 181 | int board_fix_fdt(void *rw_fdt_blob) |
| 182 | { |
| 183 | int node = -1; |
| 184 | |
| 185 | switch (malta_sys_con()) { |
| 186 | case SYSCON_GT64120: |
| 187 | node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH); |
| 188 | break; |
| 189 | default: |
| 190 | case SYSCON_MSC01: |
| 191 | node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH); |
| 192 | break; |
| 193 | } |
| 194 | |
| 195 | return fdt_status_okay(rw_fdt_blob, node); |
| 196 | } |
| 197 | #endif |
| 198 | |
Daniel Schwierzeck | 09d32c0 | 2021-07-15 20:54:00 +0200 | [diff] [blame] | 199 | int board_early_init_r(void) |
| 200 | { |
| 201 | struct udevice *dev; |
| 202 | int ret; |
| 203 | |
| 204 | pci_init(); |
| 205 | |
| 206 | ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL, |
| 207 | PCI_DEVICE_ID_INTEL_82371AB_0, 0, &dev); |
| 208 | if (ret) |
| 209 | panic("Failed to find PIIX4 PCI bridge\n"); |
| 210 | |
| 211 | /* setup PCI interrupt routing */ |
| 212 | dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10); |
| 213 | dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10); |
| 214 | dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11); |
| 215 | dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11); |
| 216 | |
| 217 | /* mux SERIRQ onto SERIRQ pin */ |
| 218 | dm_pci_clrset_config32(dev, PCI_CFG_PIIX4_GENCFG, 0, |
| 219 | PCI_CFG_PIIX4_GENCFG_SERIRQ); |
| 220 | |
| 221 | /* enable SERIRQ - Linux currently depends upon this */ |
| 222 | dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0, |
| 223 | PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT); |
| 224 | |
| 225 | ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL, |
| 226 | PCI_DEVICE_ID_INTEL_82371AB, 0, &dev); |
| 227 | if (ret) |
| 228 | panic("Failed to find PIIX4 IDE controller\n"); |
| 229 | |
| 230 | /* enable bus master & IO access */ |
| 231 | dm_pci_clrset_config32(dev, PCI_COMMAND, 0, |
| 232 | PCI_COMMAND_MASTER | PCI_COMMAND_IO); |
| 233 | |
| 234 | /* set latency */ |
| 235 | dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); |
| 236 | |
| 237 | /* enable IDE/ATA */ |
| 238 | dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI, |
| 239 | PCI_CFG_PIIX4_IDETIM_IDE); |
| 240 | dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC, |
| 241 | PCI_CFG_PIIX4_IDETIM_IDE); |
| 242 | |
| 243 | return 0; |
| 244 | } |