Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2021 Gateworks Corporation |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <cpu_func.h> |
| 8 | #include <hang.h> |
| 9 | #include <i2c.h> |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 10 | #include <init.h> |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 11 | #include <spl.h> |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 12 | #include <asm/mach-imx/gpio.h> |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 13 | #include <asm/arch/clock.h> |
| 14 | #include <asm/arch/imx8mm_pins.h> |
Tim Harvey | 1a50e74 | 2022-02-11 10:48:56 -0800 | [diff] [blame] | 15 | #include <asm/arch/imx8mn_pins.h> |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 16 | #include <asm/arch/imx8mp_pins.h> |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 17 | #include <asm/arch/sys_proto.h> |
| 18 | #include <asm/mach-imx/boot_mode.h> |
| 19 | #include <asm/arch/ddr.h> |
| 20 | #include <asm-generic/gpio.h> |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 21 | #include <dm/uclass.h> |
| 22 | #include <dm/device.h> |
Tim Harvey | d4daeaa | 2022-04-13 08:56:40 -0700 | [diff] [blame] | 23 | #include <linux/delay.h> |
Tim Harvey | 1b7fbf6 | 2021-06-30 16:50:02 -0700 | [diff] [blame] | 24 | #include <power/bd71837.h> |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 25 | #include <power/mp5416.h> |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 26 | #include <power/pca9450.h> |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 27 | |
Tim Harvey | d4daeaa | 2022-04-13 08:56:40 -0700 | [diff] [blame] | 28 | #include "eeprom.h" |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 29 | #include "lpddr4_timing.h" |
| 30 | |
| 31 | #define PCIE_RSTN IMX_GPIO_NR(4, 6) |
| 32 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 33 | static void spl_dram_init(int size) |
| 34 | { |
| 35 | struct dram_timing_info *dram_timing; |
| 36 | |
| 37 | switch (size) { |
Tim Harvey | 1a50e74 | 2022-02-11 10:48:56 -0800 | [diff] [blame] | 38 | #ifdef CONFIG_IMX8MM |
Tim Harvey | 5cc5e19 | 2022-02-18 15:19:33 -0800 | [diff] [blame] | 39 | case 512: |
| 40 | dram_timing = &dram_timing_512mb; |
| 41 | break; |
| 42 | case 1024: |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 43 | dram_timing = &dram_timing_1gb; |
| 44 | break; |
Tim Harvey | 5cc5e19 | 2022-02-18 15:19:33 -0800 | [diff] [blame] | 45 | case 2048: |
Tim Harvey | 6603b5e | 2021-07-27 15:19:41 -0700 | [diff] [blame] | 46 | dram_timing = &dram_timing_2gb; |
| 47 | break; |
Tim Harvey | 5cc5e19 | 2022-02-18 15:19:33 -0800 | [diff] [blame] | 48 | case 4096: |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 49 | dram_timing = &dram_timing_4gb; |
| 50 | break; |
| 51 | default: |
Tim Harvey | 5cc5e19 | 2022-02-18 15:19:33 -0800 | [diff] [blame] | 52 | printf("Unknown DDR configuration: %d MiB\n", size); |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 53 | dram_timing = &dram_timing_1gb; |
Tim Harvey | 5cc5e19 | 2022-02-18 15:19:33 -0800 | [diff] [blame] | 54 | size = 1024; |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 55 | #elif CONFIG_IMX8MN |
Tim Harvey | 5cc5e19 | 2022-02-18 15:19:33 -0800 | [diff] [blame] | 56 | case 1024: |
Tim Harvey | 1a50e74 | 2022-02-11 10:48:56 -0800 | [diff] [blame] | 57 | dram_timing = &dram_timing_1gb_single_die; |
| 58 | break; |
Tim Harvey | 5cc5e19 | 2022-02-18 15:19:33 -0800 | [diff] [blame] | 59 | case 2048: |
Tim Harvey | d4daeaa | 2022-04-13 08:56:40 -0700 | [diff] [blame] | 60 | if (!strcmp(eeprom_get_model(), "GW7902-SP466-A") || |
| 61 | !strcmp(eeprom_get_model(), "GW7902-SP466-B")) { |
Tim Harvey | 1a50e74 | 2022-02-11 10:48:56 -0800 | [diff] [blame] | 62 | dram_timing = &dram_timing_2gb_dual_die; |
| 63 | } else { |
| 64 | dram_timing = &dram_timing_2gb_single_die; |
| 65 | } |
| 66 | break; |
| 67 | default: |
Tim Harvey | 5cc5e19 | 2022-02-18 15:19:33 -0800 | [diff] [blame] | 68 | printf("Unknown DDR configuration: %d MiB\n", size); |
Tim Harvey | 1a50e74 | 2022-02-11 10:48:56 -0800 | [diff] [blame] | 69 | dram_timing = &dram_timing_2gb_dual_die; |
Tim Harvey | 5cc5e19 | 2022-02-18 15:19:33 -0800 | [diff] [blame] | 70 | size = 2048; |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 71 | #elif CONFIG_IMX8MP |
| 72 | case 4096: |
| 73 | dram_timing = &dram_timing_4gb_dual_die; |
| 74 | break; |
| 75 | default: |
| 76 | printf("Unknown DDR configuration: %d GiB\n", size); |
| 77 | dram_timing = &dram_timing_4gb_dual_die; |
| 78 | size = 4096; |
Tim Harvey | 1a50e74 | 2022-02-11 10:48:56 -0800 | [diff] [blame] | 79 | #endif |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 80 | } |
| 81 | |
Tim Harvey | 5cc5e19 | 2022-02-18 15:19:33 -0800 | [diff] [blame] | 82 | printf("DRAM : LPDDR4 "); |
| 83 | if (size > 512) |
| 84 | printf("%d GiB\n", size / 1024); |
| 85 | else |
| 86 | printf("%d MiB\n", size); |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 87 | ddr_init(dram_timing); |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 88 | } |
| 89 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 90 | #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) |
| 91 | |
Tim Harvey | 1a50e74 | 2022-02-11 10:48:56 -0800 | [diff] [blame] | 92 | #ifdef CONFIG_IMX8MM |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 93 | static iomux_v3_cfg_t const wdog_pads[] = { |
| 94 | IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| 95 | }; |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 96 | #elif CONFIG_IMX8MN |
Tim Harvey | 1a50e74 | 2022-02-11 10:48:56 -0800 | [diff] [blame] | 97 | static const iomux_v3_cfg_t wdog_pads[] = { |
| 98 | IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| 99 | }; |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 100 | #elif CONFIG_IMX8MP |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 101 | static const iomux_v3_cfg_t wdog_pads[] = { |
| 102 | MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| 103 | }; |
Tim Harvey | 1a50e74 | 2022-02-11 10:48:56 -0800 | [diff] [blame] | 104 | #endif |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 105 | |
| 106 | int board_early_init_f(void) |
| 107 | { |
| 108 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |
| 109 | |
| 110 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
| 111 | |
| 112 | set_wdog_reset(wdog); |
| 113 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | /* |
| 118 | * Model specific PMIC adjustments necessary prior to DRAM init |
| 119 | * |
| 120 | * Note that we can not use pmic dm drivers here as we have a generic |
| 121 | * venice dt that does not have board-specific pmic's defined. |
| 122 | * |
Tim Harvey | 1b7fbf6 | 2021-06-30 16:50:02 -0700 | [diff] [blame] | 123 | * Instead we must use dm_i2c so we a helpers to give us |
| 124 | * clrsetbit functions we would otherwise have if we could use PMIC dm |
| 125 | * drivers. |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 126 | */ |
Tim Harvey | 1b7fbf6 | 2021-06-30 16:50:02 -0700 | [diff] [blame] | 127 | static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) |
| 128 | { |
| 129 | int ret; |
| 130 | u8 val; |
| 131 | |
| 132 | ret = dm_i2c_read(dev, reg, &val, 1); |
| 133 | if (ret) |
| 134 | return ret; |
| 135 | val = (val & ~clr) | set; |
| 136 | |
| 137 | return dm_i2c_write(dev, reg, &val, 1); |
| 138 | } |
| 139 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 140 | static int power_init_board(void) |
| 141 | { |
Tim Harvey | d4daeaa | 2022-04-13 08:56:40 -0700 | [diff] [blame] | 142 | const char *model = eeprom_get_model(); |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 143 | struct udevice *bus; |
| 144 | struct udevice *dev; |
| 145 | int ret; |
| 146 | |
| 147 | if ((!strncmp(model, "GW71", 4)) || |
| 148 | (!strncmp(model, "GW72", 4)) || |
| 149 | (!strncmp(model, "GW73", 4))) { |
Tim Harvey | d541927 | 2021-07-27 15:19:38 -0700 | [diff] [blame] | 150 | ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 151 | if (ret) { |
| 152 | printf("PMIC : failed I2C1 probe: %d\n", ret); |
| 153 | return ret; |
| 154 | } |
| 155 | ret = dm_i2c_probe(bus, 0x69, 0, &dev); |
| 156 | if (ret) { |
| 157 | printf("PMIC : failed probe: %d\n", ret); |
| 158 | return ret; |
| 159 | } |
| 160 | puts("PMIC : MP5416\n"); |
| 161 | |
| 162 | /* set VDD_ARM SW3 to 0.92V for 1.6GHz */ |
| 163 | dm_i2c_reg_write(dev, MP5416_VSET_SW3, |
| 164 | BIT(7) | MP5416_VSET_SW3_SVAL(920000)); |
| 165 | } |
| 166 | |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 167 | else if (!strncmp(model, "GW74", 4)) { |
| 168 | ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); |
| 169 | if (ret) { |
| 170 | printf("PMIC : failed I2C1 probe: %d\n", ret); |
| 171 | return ret; |
| 172 | } |
| 173 | ret = dm_i2c_probe(bus, 0x25, 0, &dev); |
| 174 | if (ret) { |
| 175 | printf("PMIC : failed probe: %d\n", ret); |
| 176 | return ret; |
| 177 | } |
| 178 | puts("PMIC : PCA9450\n"); |
| 179 | |
| 180 | /* BUCKxOUT_DVS0/1 control BUCK123 output */ |
| 181 | dm_i2c_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); |
| 182 | |
| 183 | /* Buck 1 DVS control through PMIC_STBY_REQ */ |
| 184 | dm_i2c_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); |
| 185 | |
| 186 | /* Set DVS1 to 0.8v for suspend */ |
| 187 | dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10); |
| 188 | |
| 189 | /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ |
| 190 | dm_i2c_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C); |
| 191 | |
| 192 | /* VDD_DRAM off in suspend: B1_ENMODE=10 */ |
| 193 | dm_i2c_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a); |
| 194 | |
| 195 | /* set VDD_SNVS_0V8 from default 0.85V */ |
| 196 | dm_i2c_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); |
| 197 | |
| 198 | /* set WDOG_B_CFG to cold reset */ |
| 199 | dm_i2c_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); |
| 200 | } |
| 201 | |
Tim Harvey | 6603b5e | 2021-07-27 15:19:41 -0700 | [diff] [blame] | 202 | else if ((!strncmp(model, "GW7901", 6)) || |
| 203 | (!strncmp(model, "GW7902", 6))) { |
| 204 | if (!strncmp(model, "GW7901", 6)) |
| 205 | ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus); |
| 206 | else |
| 207 | ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); |
Tim Harvey | 1b7fbf6 | 2021-06-30 16:50:02 -0700 | [diff] [blame] | 208 | if (ret) { |
| 209 | printf("PMIC : failed I2C2 probe: %d\n", ret); |
| 210 | return ret; |
| 211 | } |
| 212 | ret = dm_i2c_probe(bus, 0x4b, 0, &dev); |
| 213 | if (ret) { |
| 214 | printf("PMIC : failed probe: %d\n", ret); |
| 215 | return ret; |
| 216 | } |
| 217 | puts("PMIC : BD71847\n"); |
| 218 | |
| 219 | /* unlock the PMIC regs */ |
| 220 | dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x1); |
| 221 | |
| 222 | /* set switchers to forced PWM mode */ |
| 223 | dm_i2c_clrsetbits(dev, BD718XX_BUCK1_CTRL, 0, 0x8); |
| 224 | dm_i2c_clrsetbits(dev, BD718XX_BUCK2_CTRL, 0, 0x8); |
| 225 | dm_i2c_clrsetbits(dev, BD718XX_1ST_NODVS_BUCK_CTRL, 0, 0x8); |
| 226 | dm_i2c_clrsetbits(dev, BD718XX_2ND_NODVS_BUCK_CTRL, 0, 0x8); |
| 227 | dm_i2c_clrsetbits(dev, BD718XX_3RD_NODVS_BUCK_CTRL, 0, 0x8); |
| 228 | dm_i2c_clrsetbits(dev, BD718XX_4TH_NODVS_BUCK_CTRL, 0, 0x8); |
| 229 | |
| 230 | /* increase VDD_0P95 (VDD_GPU/VPU/DRAM) to 0.975v for 1.5Ghz DDR */ |
| 231 | dm_i2c_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); |
| 232 | |
| 233 | /* increase VDD_SOC to 0.85v before first DRAM access */ |
| 234 | dm_i2c_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); |
| 235 | |
| 236 | /* increase VDD_ARM to 0.92v for 800 and 1600Mhz */ |
| 237 | dm_i2c_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0x16); |
| 238 | |
| 239 | /* Lock the PMIC regs */ |
| 240 | dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x11); |
| 241 | } |
| 242 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | void board_init_f(ulong dummy) |
| 247 | { |
| 248 | struct udevice *dev; |
| 249 | int ret; |
| 250 | int dram_sz; |
| 251 | |
| 252 | arch_cpu_init(); |
| 253 | |
| 254 | init_uart_clk(1); |
| 255 | |
| 256 | board_early_init_f(); |
| 257 | |
| 258 | timer_init(); |
| 259 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 260 | /* Clear the BSS. */ |
| 261 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 262 | |
| 263 | ret = spl_early_init(); |
| 264 | if (ret) { |
| 265 | debug("spl_early_init() failed: %d\n", ret); |
| 266 | hang(); |
| 267 | } |
| 268 | |
Tim Harvey | 91db793 | 2022-04-29 12:36:25 -0700 | [diff] [blame] | 269 | preloader_console_init(); |
| 270 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 271 | enable_tzc380(); |
| 272 | |
| 273 | /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */ |
| 274 | gpio_request(PCIE_RSTN, "perst#"); |
| 275 | gpio_direction_output(PCIE_RSTN, 0); |
| 276 | |
Tim Harvey | d4daeaa | 2022-04-13 08:56:40 -0700 | [diff] [blame] | 277 | /* |
| 278 | * probe GSC device |
| 279 | * |
| 280 | * On a board with a missing/depleted backup battery for GSC, the |
| 281 | * board may be ready to probe the GSC before its firmware is |
| 282 | * running. We will wait here indefinately for the GSC EEPROM. |
| 283 | */ |
| 284 | #ifdef CONFIG_IMX8MN |
| 285 | /* |
| 286 | * IMX8MN boots quicker than IMX8MM and exposes issue |
| 287 | * where because GSC I2C state machine isn't running and its |
| 288 | * SCL/SDA are driven low the I2C driver spams 'Arbitration lost' |
| 289 | * I2C errors. |
| 290 | * |
| 291 | * TODO: Put a loop here that somehow waits for I2C CLK/DAT to be high |
| 292 | */ |
| 293 | mdelay(50); |
| 294 | #endif |
| 295 | while (1) { |
| 296 | if (!uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev)) |
| 297 | break; |
| 298 | mdelay(1); |
| 299 | } |
| 300 | dram_sz = eeprom_init(0); |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 301 | |
| 302 | /* PMIC */ |
| 303 | power_init_board(); |
| 304 | |
| 305 | /* DDR initialization */ |
| 306 | spl_dram_init(dram_sz); |
| 307 | |
| 308 | board_init_r(NULL, 0); |
| 309 | } |
| 310 | |
| 311 | /* determine prioritized order of boot devices to load U-Boot from */ |
| 312 | void board_boot_order(u32 *spl_boot_list) |
| 313 | { |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 314 | int i = 0; |
| 315 | |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 316 | /* |
| 317 | * If the SPL was loaded via serial loader, we try to get |
| 318 | * U-Boot proper via USB SDP. |
| 319 | */ |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 320 | if (spl_boot_device() == BOOT_DEVICE_BOARD) { |
| 321 | #ifdef CONFIG_IMX8MM |
| 322 | spl_boot_list[i++] = BOOT_DEVICE_BOARD; |
| 323 | #else |
| 324 | spl_boot_list[i++] = BOOT_DEVICE_BOOTROM; |
| 325 | #endif |
| 326 | } |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 327 | |
| 328 | /* we have only eMMC in default venice dt */ |
Tim Harvey | 0f5717f | 2022-04-13 11:31:09 -0700 | [diff] [blame] | 329 | spl_boot_list[i++] = BOOT_DEVICE_MMC1; |
Tim Harvey | 256dba0 | 2021-03-02 14:00:21 -0800 | [diff] [blame] | 330 | } |
| 331 | |
| 332 | /* return boot device based on where the SPL was loaded from */ |
| 333 | int spl_board_boot_device(enum boot_device boot_dev_spl) |
| 334 | { |
| 335 | switch (boot_dev_spl) { |
| 336 | case USB_BOOT: |
| 337 | return BOOT_DEVICE_BOARD; |
| 338 | /* SDHC2 */ |
| 339 | case SD2_BOOT: |
| 340 | case MMC2_BOOT: |
| 341 | return BOOT_DEVICE_MMC1; |
| 342 | /* SDHC3 */ |
| 343 | case SD3_BOOT: |
| 344 | case MMC3_BOOT: |
| 345 | return BOOT_DEVICE_MMC2; |
| 346 | default: |
| 347 | return BOOT_DEVICE_NONE; |
| 348 | } |
| 349 | } |
Tim Harvey | 724d10a | 2022-03-08 10:45:39 -0800 | [diff] [blame] | 350 | |
| 351 | const char *spl_board_loader_name(u32 boot_device) |
| 352 | { |
| 353 | switch (boot_device) { |
| 354 | /* SDHC2 */ |
| 355 | case BOOT_DEVICE_MMC1: |
| 356 | return "eMMC"; |
| 357 | /* SDHC3 */ |
| 358 | case BOOT_DEVICE_MMC2: |
| 359 | return "SD card"; |
| 360 | default: |
| 361 | return NULL; |
| 362 | } |
| 363 | } |