| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0+ |
| Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 2 | # |
| 3 | # Copyright (C) 2015 Google, Inc |
| Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 4 | |
| 5 | config INTEL_BAYTRAIL |
| 6 | bool |
| Bin Meng | 7676370 | 2018-06-12 08:36:20 -0700 | [diff] [blame] | 7 | select HAVE_FSP |
| 8 | select ARCH_MISC_INIT |
| Bin Meng | f647599 | 2017-08-17 01:10:43 -0700 | [diff] [blame] | 9 | select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED |
| Tom Rini | 7d3684a | 2023-01-16 15:46:49 -0500 | [diff] [blame^] | 10 | select DM_EVENT |
| Bin Meng | 7676370 | 2018-06-12 08:36:20 -0700 | [diff] [blame] | 11 | imply HAVE_INTEL_ME |
| Bin Meng | 1949a9a | 2017-07-30 06:23:14 -0700 | [diff] [blame] | 12 | imply ENABLE_MRC_CACHE |
| Bin Meng | 73f5bc1 | 2017-07-30 19:24:02 -0700 | [diff] [blame] | 13 | imply AHCI_PCI |
| Bin Meng | 2c00e03 | 2017-07-30 06:23:17 -0700 | [diff] [blame] | 14 | imply ICH_SPI |
| Bin Meng | ce9d1b0 | 2017-07-30 06:23:28 -0700 | [diff] [blame] | 15 | imply INTEL_ICH6_GPIO |
| Bin Meng | c253c3f | 2018-06-10 06:25:01 -0700 | [diff] [blame] | 16 | imply PINCTRL_ICH6 |
| Bin Meng | 2c00e03 | 2017-07-30 06:23:17 -0700 | [diff] [blame] | 17 | imply MMC |
| 18 | imply MMC_PCI |
| 19 | imply MMC_SDHCI |
| 20 | imply MMC_SDHCI_SDMA |
| 21 | imply SCSI |
| Tuomas Tynkkynen | edf9f62 | 2017-12-08 15:36:19 +0200 | [diff] [blame] | 22 | imply SCSI_AHCI |
| Bin Meng | 2c00e03 | 2017-07-30 06:23:17 -0700 | [diff] [blame] | 23 | imply SPI_FLASH |
| 24 | imply SYS_NS16550 |
| Bin Meng | 5b5d173 | 2017-07-30 06:23:27 -0700 | [diff] [blame] | 25 | imply USB |
| 26 | imply USB_EHCI_HCD |
| 27 | imply USB_XHCI_HCD |
| Bin Meng | 2c00e03 | 2017-07-30 06:23:17 -0700 | [diff] [blame] | 28 | imply VIDEO_VESA |
| Bin Meng | fe8d45d | 2016-06-14 21:33:23 -0700 | [diff] [blame] | 29 | |
| 30 | if INTEL_BAYTRAIL |
| 31 | config INTERNAL_UART |
| 32 | bool "Enable the SoC integrated legacy UART" |
| 33 | help |
| 34 | There is a legacy UART integrated into the Bay Trail SoC. |
| 35 | A maximum baud rate of 115200 bps is supported. For this |
| 36 | reason, it is recommended that the UART port be used for |
| 37 | debug purposes only, eg: U-Boot console. |
| 38 | |
| Bin Meng | 273d0ec | 2017-06-01 03:41:13 -0700 | [diff] [blame] | 39 | config DEBUG_UART |
| 40 | bool |
| 41 | select DEBUG_UART_BOARD_INIT |
| 42 | |
| Bin Meng | fe8d45d | 2016-06-14 21:33:23 -0700 | [diff] [blame] | 43 | endif |