| developer | f4d0d2b | 2020-11-12 16:36:10 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 MediaTek Inc. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef _DT_BINDINGS_MT7620_CLK_H_ |
| 9 | #define _DT_BINDINGS_MT7620_CLK_H_ |
| 10 | |
| 11 | /* Base clocks */ |
| 12 | #define CLK_SYS 34 |
| 13 | #define CLK_CPU 33 |
| 14 | #define CLK_XTAL 32 |
| 15 | |
| 16 | /* Peripheral clocks */ |
| 17 | #define CLK_SDHC 30 |
| 18 | #define CLK_MIPS_CNT 28 |
| 19 | #define CLK_PCIE 26 |
| 20 | #define CLK_UPHY_12M 25 |
| 21 | #define CLK_EPHY 24 |
| 22 | #define CLK_ESW 23 |
| 23 | #define CLK_UPHY_48M 22 |
| 24 | #define CLK_FE 21 |
| 25 | #define CLK_UARTL 19 |
| 26 | #define CLK_SPI 18 |
| 27 | #define CLK_I2S 17 |
| 28 | #define CLK_I2C 16 |
| 29 | #define CLK_NAND 15 |
| 30 | #define CLK_GDMA 14 |
| 31 | #define CLK_PIO 13 |
| 32 | #define CLK_UARTF 12 |
| 33 | #define CLK_PCM 11 |
| 34 | #define CLK_MC 10 |
| 35 | #define CLK_INTC 9 |
| 36 | #define CLK_TIMER 8 |
| 37 | #define CLK_GE2 7 |
| 38 | #define CLK_GE1 6 |
| 39 | |
| 40 | #endif /* _DT_BINDINGS_MT7620_CLK_H_ */ |