Daniel Hellstrom | 9d7c6b2 | 2008-03-28 09:47:00 +0100 | [diff] [blame] | 1 | /* SPARC I/O definitions |
| 2 | * |
| 3 | * (C) Copyright 2007 |
| 4 | * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Daniel Hellstrom | 9d7c6b2 | 2008-03-28 09:47:00 +0100 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef _SPARC_IO_H |
| 10 | #define _SPARC_IO_H |
| 11 | |
| 12 | /* Nothing to sync, total store ordering (TSO)... */ |
| 13 | #define sync() |
| 14 | |
| 15 | /* Forces a cache miss on read/load. |
| 16 | * On some architectures we need to bypass the cache when reading |
| 17 | * I/O registers so that we are not reading the same status word |
| 18 | * over and over again resulting in a hang (until an IRQ if lucky) |
| 19 | * |
| 20 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 21 | #ifndef CONFIG_SYS_HAS_NO_CACHE |
Daniel Hellstrom | 9d7c6b2 | 2008-03-28 09:47:00 +0100 | [diff] [blame] | 22 | #define READ_BYTE(var) SPARC_NOCACHE_READ_BYTE((unsigned int)(var)) |
| 23 | #define READ_HWORD(var) SPARC_NOCACHE_READ_HWORD((unsigned int)(var)) |
| 24 | #define READ_WORD(var) SPARC_NOCACHE_READ((unsigned int)(var)) |
| 25 | #define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)(var)) |
| 26 | #else |
| 27 | #define READ_BYTE(var) (var) |
| 28 | #define READ_HWORD(var) (var) |
| 29 | #define READ_WORD(var) (var) |
| 30 | #define READ_DWORD(var) (var) |
| 31 | #endif |
| 32 | |
| 33 | /* |
| 34 | * Generic virtual read/write. |
| 35 | */ |
| 36 | #define __arch_getb(a) (READ_BYTE(a)) |
| 37 | #define __arch_getw(a) (READ_HWORD(a)) |
| 38 | #define __arch_getl(a) (READ_WORD(a)) |
| 39 | #define __arch_getq(a) (READ_DWORD(a)) |
| 40 | |
| 41 | #define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) |
| 42 | #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) |
| 43 | #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) |
| 44 | |
| 45 | #define __raw_writeb(v,a) __arch_putb(v,a) |
| 46 | #define __raw_writew(v,a) __arch_putw(v,a) |
| 47 | #define __raw_writel(v,a) __arch_putl(v,a) |
| 48 | |
| 49 | #define __raw_readb(a) __arch_getb(a) |
| 50 | #define __raw_readw(a) __arch_getw(a) |
| 51 | #define __raw_readl(a) __arch_getl(a) |
| 52 | #define __raw_readq(a) __arch_getq(a) |
| 53 | |
| 54 | /* |
| 55 | * Given a physical address and a length, return a virtual address |
| 56 | * that can be used to access the memory range with the caching |
| 57 | * properties specified by "flags". |
| 58 | */ |
Daniel Hellstrom | 9d7c6b2 | 2008-03-28 09:47:00 +0100 | [diff] [blame] | 59 | |
| 60 | #define MAP_NOCACHE (0) |
| 61 | #define MAP_WRCOMBINE (0) |
| 62 | #define MAP_WRBACK (0) |
| 63 | #define MAP_WRTHROUGH (0) |
| 64 | |
| 65 | static inline void *map_physmem(phys_addr_t paddr, unsigned long len, |
| 66 | unsigned long flags) |
| 67 | { |
| 68 | return (void *)paddr; |
| 69 | } |
| 70 | |
| 71 | /* |
| 72 | * Take down a mapping set up by map_physmem(). |
| 73 | */ |
| 74 | static inline void unmap_physmem(void *vaddr, unsigned long flags) |
| 75 | { |
| 76 | |
| 77 | } |
| 78 | |
Kumar Gala | 9364a67 | 2008-12-13 17:20:27 -0600 | [diff] [blame] | 79 | static inline phys_addr_t virt_to_phys(void * vaddr) |
| 80 | { |
| 81 | return (phys_addr_t)(vaddr); |
| 82 | } |
| 83 | |
Daniel Hellstrom | 9d7c6b2 | 2008-03-28 09:47:00 +0100 | [diff] [blame] | 84 | #endif |