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git01.mediatek.com / filogic / uboot / 7c767adb003ad18b096ad61e323cfeeb88b85db2 / . / post / lib_powerpc / cpu.c
blob: 109be38e16669da726e176f25ba644bfda7bc482 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]2/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]5 */
6
7#include <common.h>
8
9/*
10 * CPU test
11 *
12 * This test checks the arithmetic logic unit (ALU) of CPU.
13 * It tests independently various groups of instructions using
14 * run-time modification of the code to reduce the memory footprint.
15 * For more details refer to post/cpu/ *.c files.
16 */
17
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]18#include <watchdog.h>
19#include <post.h>
Stefan Roesebc5591f2007-10-31 20:51:10 +0100[diff] [blame]20#include <asm/mmu.h>
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]21
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]22#if CONFIG_POST & CONFIG_SYS_POST_CPU
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]23
24extern int cpu_post_test_cmp (void);
25extern int cpu_post_test_cmpi (void);
26extern int cpu_post_test_two (void);
27extern int cpu_post_test_twox (void);
28extern int cpu_post_test_three (void);
29extern int cpu_post_test_threex (void);
30extern int cpu_post_test_threei (void);
31extern int cpu_post_test_andi (void);
32extern int cpu_post_test_srawi (void);
33extern int cpu_post_test_rlwnm (void);
34extern int cpu_post_test_rlwinm (void);
35extern int cpu_post_test_rlwimi (void);
36extern int cpu_post_test_store (void);
37extern int cpu_post_test_load (void);
38extern int cpu_post_test_cr (void);
39extern int cpu_post_test_b (void);
40extern int cpu_post_test_multi (void);
41extern int cpu_post_test_string (void);
42extern int cpu_post_test_complex (void);
43
44ulong cpu_post_makecr (long v)
45{
46 ulong cr = 0;
47
48 if (v < 0)
49 cr |= 0x80000000;
50 if (v > 0)
51 cr |= 0x40000000;
52 if (v == 0)
53 cr |= 0x20000000;
54
55 return cr;
56}
57
58int cpu_post_test (int flags)
59{
60 int ic = icache_status ();
61 int ret = 0;
62
63 WATCHDOG_RESET();
64 if (ic)
65 icache_disable ();
66
67 if (ret == 0)
68 ret = cpu_post_test_cmp ();
69 if (ret == 0)
70 ret = cpu_post_test_cmpi ();
71 if (ret == 0)
72 ret = cpu_post_test_two ();
73 if (ret == 0)
74 ret = cpu_post_test_twox ();
75 WATCHDOG_RESET();
76 if (ret == 0)
77 ret = cpu_post_test_three ();
78 if (ret == 0)
79 ret = cpu_post_test_threex ();
80 if (ret == 0)
81 ret = cpu_post_test_threei ();
82 if (ret == 0)
83 ret = cpu_post_test_andi ();
84 WATCHDOG_RESET();
85 if (ret == 0)
86 ret = cpu_post_test_srawi ();
87 if (ret == 0)
88 ret = cpu_post_test_rlwnm ();
89 if (ret == 0)
90 ret = cpu_post_test_rlwinm ();
91 if (ret == 0)
92 ret = cpu_post_test_rlwimi ();
93 WATCHDOG_RESET();
94 if (ret == 0)
95 ret = cpu_post_test_store ();
96 if (ret == 0)
97 ret = cpu_post_test_load ();
98 if (ret == 0)
99 ret = cpu_post_test_cr ();
100 if (ret == 0)
101 ret = cpu_post_test_b ();
102 WATCHDOG_RESET();
103 if (ret == 0)
104 ret = cpu_post_test_multi ();
105 WATCHDOG_RESET();
106 if (ret == 0)
107 ret = cpu_post_test_string ();
108 if (ret == 0)
109 ret = cpu_post_test_complex ();
110 WATCHDOG_RESET();
111
112 if (ic)
113 icache_enable ();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]114
115 WATCHDOG_RESET();
116
117 return ret;
118}
119
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]120#endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */