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git01.mediatek.com / filogic / uboot / 7c767adb003ad18b096ad61e323cfeeb88b85db2 / . / drivers / reset / reset-rockchip.c
blob: af0713404959e28a78fdba76ab52c2f6210b5e5b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Elaine Zhang6e9a3a72017-12-19 18:22:37 +0800[diff] [blame]2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
Elaine Zhang6e9a3a72017-12-19 18:22:37 +0800[diff] [blame]4 */
5
6#include <common.h>
7#include <dm.h>
8#include <reset-uclass.h>
9#include <linux/io.h>
10#include <asm/arch/hardware.h>
11#include <dm/lists.h>
12/*
13 * Each reg has 16 bits reset signal for devices
14 * Note: Not including rk2818 and older SoCs
15 */
16#define ROCKCHIP_RESET_NUM_IN_REG 16
17
18struct rockchip_reset_priv {
19 void __iomem *base;
20 /* Rockchip reset reg locate at cru controller */
21 u32 reset_reg_offset;
22 /* Rockchip reset reg number */
23 u32 reset_reg_num;
24};
25
26static int rockchip_reset_request(struct reset_ctl *reset_ctl)
27{
28 struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
29
30 debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
31 reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
32
33 if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
34 return -EINVAL;
35
36 return 0;
37}
38
39static int rockchip_reset_free(struct reset_ctl *reset_ctl)
40{
41 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
42 reset_ctl->dev, reset_ctl->id);
43
44 return 0;
45}
46
47static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
48{
49 struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
50 int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
51 int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
52
53 debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
54 reset_ctl, reset_ctl->dev, reset_ctl->id,
55 priv->base + (bank * 4));
56
57 rk_setreg(priv->base + (bank * 4), BIT(offset));
58
59 return 0;
60}
61
62static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
63{
64 struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
65 int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
66 int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
67
68 debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
69 reset_ctl, reset_ctl->dev, reset_ctl->id,
70 priv->base + (bank * 4));
71
72 rk_clrreg(priv->base + (bank * 4), BIT(offset));
73
74 return 0;
75}
76
77struct reset_ops rockchip_reset_ops = {
78 .request = rockchip_reset_request,
79 .free = rockchip_reset_free,
80 .rst_assert = rockchip_reset_assert,
81 .rst_deassert = rockchip_reset_deassert,
82};
83
84static int rockchip_reset_probe(struct udevice *dev)
85{
86 struct rockchip_reset_priv *priv = dev_get_priv(dev);
87 fdt_addr_t addr;
88 fdt_size_t size;
89
90 addr = dev_read_addr_size(dev, "reg", &size);
91 if (addr == FDT_ADDR_T_NONE)
92 return -EINVAL;
93
94 if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0))
95 return -EINVAL;
96
97 addr += priv->reset_reg_offset;
98 priv->base = ioremap(addr, size);
99
100 debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__,
101 priv->base, priv->reset_reg_offset, priv->reset_reg_num);
102
103 return 0;
104}
105
106int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
107{
108 struct udevice *rst_dev;
109 struct rockchip_reset_priv *priv;
110 int ret;
111
112 ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset",
113 dev_ofnode(pdev), &rst_dev);
114 if (ret) {
115 debug("Warning: No rockchip reset driver: ret=%d\n", ret);
116 return ret;
117 }
118 priv = malloc(sizeof(struct rockchip_reset_priv));
119 priv->reset_reg_offset = reg_offset;
120 priv->reset_reg_num = reg_number;
121 rst_dev->priv = priv;
122
123 return 0;
124}
125
126U_BOOT_DRIVER(rockchip_reset) = {
127 .name = "rockchip_reset",
128 .id = UCLASS_RESET,
129 .probe = rockchip_reset_probe,
130 .ops = &rockchip_reset_ops,
131 .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv),
132};