| Simon Glass | 75659ac | 2019-04-25 21:58:52 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| Simon Glass | 202a096 | 2019-09-25 08:11:44 -0600 | [diff] [blame] | 3 | * 32-bit x86 Startup Code when running from SPL. This is the startup code in |
| 4 | * U-Boot proper, when SPL is used. |
| 5 | |
| Simon Glass | 75659ac | 2019-04-25 21:58:52 -0600 | [diff] [blame] | 6 | * Copyright 2018 Google, Inc |
| 7 | * Written by Simon Glass <sjg@chromium.org> |
| 8 | */ |
| 9 | |
| 10 | #include <config.h> |
| 11 | |
| 12 | .section .text.start |
| 13 | .code32 |
| 14 | .globl _start |
| 15 | .type _start, @function |
| 16 | _start: |
| Simon Glass | 3b01ac0 | 2020-04-26 09:13:00 -0600 | [diff] [blame] | 17 | /* |
| 18 | * If running from coreboot, CAR is no-longer available. Use the |
| 19 | * existing stack, which is large enough. |
| 20 | */ |
| 21 | call locate_coreboot_table |
| 22 | cmp $0, %eax |
| 23 | jge use_existing_stack |
| 24 | |
| Simon Glass | 75659ac | 2019-04-25 21:58:52 -0600 | [diff] [blame] | 25 | movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %eax |
| 26 | #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE |
| 27 | subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %eax |
| 28 | #endif |
| Simon Glass | 3b01ac0 | 2020-04-26 09:13:00 -0600 | [diff] [blame] | 29 | jmp 2f |
| Simon Glass | 75659ac | 2019-04-25 21:58:52 -0600 | [diff] [blame] | 30 | /* |
| Simon Glass | 3b01ac0 | 2020-04-26 09:13:00 -0600 | [diff] [blame] | 31 | * We don't subtract CONFIG_DCACHE_RAM_MRC_VAR_SIZE since memory is |
| Simon Glass | 75659ac | 2019-04-25 21:58:52 -0600 | [diff] [blame] | 32 | * already set up. This has the happy side-effect of putting gd in a |
| 33 | * new place separate from SPL, so the memset() in |
| 34 | * board_init_f_init_reserve() does not cause any problems (otherwise |
| 35 | * it would zero out the gd and crash) |
| 36 | */ |
| Simon Glass | 3b01ac0 | 2020-04-26 09:13:00 -0600 | [diff] [blame] | 37 | /* Set up memory using the existing stack */ |
| 38 | use_existing_stack: |
| 39 | mov %esp, %eax |
| 40 | 2: |
| Simon Glass | 75659ac | 2019-04-25 21:58:52 -0600 | [diff] [blame] | 41 | call board_init_f_alloc_reserve |
| 42 | mov %eax, %esp |
| 43 | |
| 44 | call board_init_f_init_reserve |
| 45 | |
| Simon Glass | 9cfd95b | 2021-03-15 18:00:31 +1300 | [diff] [blame] | 46 | #ifdef CONFIG_DEBUG_UART |
| 47 | call debug_uart_init |
| 48 | #endif |
| 49 | |
| Simon Glass | 81f1462 | 2019-10-20 21:37:55 -0600 | [diff] [blame] | 50 | call x86_cpu_reinit_f |
| Simon Glass | 75659ac | 2019-04-25 21:58:52 -0600 | [diff] [blame] | 51 | xorl %eax, %eax |
| 52 | call board_init_f |
| 53 | call board_init_f_r |
| 54 | |
| 55 | /* Should not return here */ |
| 56 | jmp . |
| 57 | |
| 58 | .globl board_init_f_r_trampoline |
| 59 | .type board_init_f_r_trampoline, @function |
| 60 | board_init_f_r_trampoline: |
| 61 | /* |
| 62 | * SPL has been executed and SDRAM has been initialised, U-Boot code |
| 63 | * has been copied into RAM, BSS has been cleared and relocation |
| 64 | * adjustments have been made. It is now time to jump into the in-RAM |
| 65 | * copy of U-Boot |
| 66 | * |
| 67 | * %eax = Address of top of new stack |
| 68 | */ |
| 69 | |
| 70 | /* Stack grows down from top of SDRAM */ |
| 71 | movl %eax, %esp |
| 72 | |
| 73 | /* Re-enter U-Boot by calling board_init_f_r() */ |
| 74 | call board_init_f_r |
| 75 | |
| 76 | die: |
| 77 | hlt |
| 78 | jmp die |
| 79 | hlt |
| 80 | |
| 81 | .align 4 |
| 82 | _dt_ucode_base_size: |
| 83 | /* These next two fields are filled in by binman */ |
| 84 | .globl ucode_base |
| 85 | ucode_base: /* Declared in microcode.h */ |
| 86 | .long 0 /* microcode base */ |
| 87 | .globl ucode_size |
| 88 | ucode_size: /* Declared in microcode.h */ |
| 89 | .long 0 /* microcode size */ |