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Holger Brunckddef8892020-02-19 19:55:14 +01001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2017-2020 ABB
4 *
5 */
6#ifndef __CONFIG_SOCFPGA_SECU1_H__
7#define __CONFIG_SOCFPGA_SECU1_H__
8
9#include <asm/arch/base_addr_ac5.h>
Simon Glassfb64e362020-05-10 11:40:09 -060010#include <linux/stringify.h>
Holger Brunckddef8892020-02-19 19:55:14 +010011
12/* Call misc_init_r */
13#define CONFIG_MISC_INIT_R
14
15#define CONFIG_HUSH_INIT_VAR
16/* Eternal oscillator */
17#define CONFIG_SYS_TIMER_RATE 40000000
18
19/* Memory configurations */
20#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */
21
22/*
23 * We use bootcounter in i2c nvram of the RTC (0x68)
24 * The offset fopr the bootcounter is 0x9e, which are
25 * the last two bytes of the 128 bytes large NVRAM in the
26 * RTC which begin at address 0x20
27 */
28#define CONFIG_SYS_I2C_RTC_ADDR 0x68
29
30/* Booting Linux */
31#define CONFIG_BOOTDELAY 2
32#define CONFIG_BOOTFILE "zImage"
33#define CONFIG_BOOTARGS \
34 "console=ttyS0," __stringify(CONFIG_BAUDRATE) \
35 " ubi.fm_autoconvert=1" \
36 " uio_pdrv_genirq.of_id=\"idq,regbank\""
37
38#define CONFIG_BOOTCOMMAND \
39 "setenv bootcmd '" \
40 "bridge enable; " \
41 "if test ${bootnum} = \"b\"; " \
42 "then run _fpga_loadsafe; " \
43 "else if test ${bootcount} -eq 4; then echo \"Switching copy...\"; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; " \
44 "run _fpga_loaduser; " \
45 "fi;" \
46 "echo \"Booting bank $bootnum\" && run userload && run userboot;" \
47 "' && " \
48 "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \
49 "saveenv && saveenv && boot;"
50
51#define CONFIG_CMDLINE_TAG
52#define CONFIG_SYS_BOOTM_LEN (64 << 20)
53
54/* Environment settings */
55#define CONFIG_ENV_OVERWRITE
56
57/*
58 * Autoboot
59 *
60 * After 45s of inactivity in the prompt, the board will reset.
61 * Set 'bootretry' in the environment to -1 to disable this behavior
62 */
63#define CONFIG_BOOT_RETRY_TIME 45
64#define CONFIG_RESET_TO_RETRY
65
66#define CONFIG_LOADADDR 0x01000000
67#define CONFIG_SYS_LOAD_ADDR CONFIG_KM_KERNEL_ADDR
68
69/*
70 * FPGA Remote Update related environment
71 *
72 * Note that since those commands access the FPGA, the HPS-to-FPGA
73 * bridges MUST have been previously enabled (for example
74 * with 'bridge enable').
75 */
76#define FPGA_RMTU_ENV \
77 "rmtu_page=0xFF29000C\0" \
78 "rmtu_reconfig=0xFF290018\0" \
79 "fpga_safebase=0x0\0" \
80 "fpga_userbase=0x2000000\0" \
81 "_fpga_loaduser=echo Loading FPGA USER image..." \
82 " && mw ${rmtu_page} ${fpga_userbase} && mw ${rmtu_reconfig} 1\0" \
83 "_fpga_loadsafe=echo Loading FPGA SAFE image..." \
84 " && mw ${rmtu_page} ${fpga_safebase} && mw ${rmtu_reconfig} 1\0" \
85
86#define CONFIG_KM_NEW_ENV \
87 "newenv=" \
88 "nand erase 0x100000 0x40000\0"
89
90#define CONFIG_KM_DEF_ENV_BOOTTARGETS \
91 "release=" \
92 "run newenv; reset\0" \
93 "develop=" \
94 "tftp 0x200000 scripts/develop-secu.txt && env import -t 0x200000 ${filesize} && saveenv && reset\0"
95
96#define CONFIG_EXTRA_ENV_SETTINGS \
97 FPGA_RMTU_ENV \
98 CONFIG_KM_DEF_ENV_BOOTTARGETS \
99 CONFIG_KM_NEW_ENV \
100 "socfpga_legacy_reset_compat=1\0" \
101 "altbootcmd=run bootcmd;\0" \
102 "bootlimit=6\0" \
103 "bootnum=1\0" \
104 "bootretry=" __stringify(CONFIG_BOOT_RETRY_TIME) "\0" \
105 "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
106 "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \
107 "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \
108 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
109 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
110 "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \
111 "userload=ubi part nand.ubi &&" \
112 "ubi check rootfs$bootnum &&" \
113 "ubi read $fdt_addr dtb$bootnum &&" \
114 "ubi read $loadaddr kernel$bootnum\0" \
115 "userboot=setenv bootargs " CONFIG_BOOTARGS \
116 " ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid" \
117 " ro rootfstype=squashfs init=sbin/preinit;" \
118 "bootz ${loadaddr} - ${fdt_addr}\0" \
119 "verify=y\0"
120
121/* The rest of the configuration is shared */
122#include <configs/socfpga_common.h>
123
124#ifdef CONFIG_SPL_NAND_SUPPORT
125#undef CONFIG_SYS_NAND_U_BOOT_OFFS
126#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
127#endif
128
129#undef CONFIG_WATCHDOG_TIMEOUT_MSECS
130#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
131
132#endif /* __CONFIG_SOCFPGA_SECU1_H__ */