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git01.mediatek.com / filogic / uboot / 7c35db760cb09483f1ec3aa667d0ab4acbd22f0b / . / arch / arm / dts / zynqmp-vpk120-revA.dts
blob: f281c7fb9fddf75cdf09bfb833f9a5e536056f79 [file] [log] [blame]
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VPK120 RevA System Controller
4 *
5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20 model = "ZynqMP System Controller on VPK120 board RevA";
21 compatible = "xlnx,zynqmp-vpk120-revA",
22 "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
23
24 aliases {
25 ethernet0 = &gem0;
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 mmc0 = &sdhci0;
29 serial0 = &uart0;
30 serial1 = &dcc;
31 spi0 = &qspi;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 nvmem0 = &eeprom;
35 };
36
37 chosen {
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>;
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
49 autorepeat;
Michal Simek518d1662024-03-08 09:40:52 +0100[diff] [blame]50 button-16 {
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]51 label = "sw16";
52 gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
53 linux,code = <BTN_MISC>;
54 wakeup-source;
55 autorepeat;
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
61 heartbeat-led { /* ds40 */
62 label = "heartbeat";
63 gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
67
Michal Simeke3157622024-01-08 10:24:45 +0100[diff] [blame]68 si5332_0: si5332-0 { /* ps_ref_clk */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <33333333>;
72 };
73
Michal Simeke3157622024-01-08 10:24:45 +0100[diff] [blame]74 si5332_1: si5332-1 { /* clk0_sgmii */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <33333333>; /* FIXME */
78 };
79
Michal Simeke3157622024-01-08 10:24:45 +0100[diff] [blame]80 si5332_2: si5332-2 { /* clk1_usb */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <27000000>;
84 };
85};
86
87&qspi { /* MIO 0-5 */
88 status = "okay";
89 flash@0 {
90 compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
91 #address-cells = <1>;
92 #size-cells = <1>;
93 reg = <0>;
94 spi-tx-bus-width = <4>;
95 spi-rx-bus-width = <4>;
96 spi-max-frequency = <108000000>;
97 partition@0 { /* for testing purpose */
98 label = "qspi";
99 reg = <0 0x4000000>;
100 };
101 };
102};
103
104&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
105 status = "okay";
106 non-removable;
107 disable-wp;
Paul Alvina1398f02024-09-25 09:03:13 +0200[diff] [blame]108 no-sd;
109 no-sdio;
110 cap-mmc-hw-reset;
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]111 bus-width = <8>;
112 xlnx,mio-bank = <0>;
113};
114
115&uart0 { /* uart0 MIO38-39 */
116 status = "okay";
117 bootph-all;
118};
119
120&gem0 {
121 status = "okay";
122 phy-handle = <&phy0>;
123 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]124 /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
Michal Simek3181a872023-10-12 14:58:47 +0200[diff] [blame]125 mdio: mdio {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
129 phy0: ethernet-phy@0 {
130 reg = <0>;
131 };
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]132 };
133};
134
135&gpio {
136 status = "okay";
137 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
138 "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
139 "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
140 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
141 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
142 "", "", "", "", "", /* 25 - 29 */
143 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
144 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
145 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
146 "", "", "", "", "", /* 45 - 49 */
147 "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
148 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
149 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
150 "", "", "", "", "", /* 65 - 69 */
151 "", "", "", "", "", /* 70 - 74 */
152 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
153 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
154 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
155 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
156 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
157 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
158 "", "", "", "", "", /* 100 - 104 */
159 "", "", "", "", "", /* 105 - 109 */
160 "", "", "", "", "", /* 110 - 114 */
161 "", "", "", "", "", /* 115 - 119 */
162 "", "", "", "", "", /* 120 - 124 */
163 "", "", "", "", "", /* 125 - 129 */
164 "", "", "", "", "", /* 130 - 134 */
165 "", "", "", "", "", /* 135 - 139 */
166 "", "", "", "", "", /* 140 - 144 */
167 "", "", "", "", "", /* 145 - 149 */
168 "", "", "", "", "", /* 150 - 154 */
169 "", "", "", "", "", /* 155 - 159 */
170 "", "", "", "", "", /* 160 - 164 */
171 "", "", "", "", "", /* 165 - 169 */
172 "", "", "", ""; /* 170 - 173 */
173};
174
175&i2c0 { /* MIO 34-35 - can't stay here */
176 status = "okay";
177 clock-frequency = <400000>;
178 pinctrl-names = "default", "gpio";
179 pinctrl-0 = <&pinctrl_i2c0_default>;
180 pinctrl-1 = <&pinctrl_i2c0_gpio>;
181 scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
182 sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
183
184 tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
185 compatible = "ti,tca6416";
186 reg = <0x20>;
187 gpio-controller; /* interrupt not connected */
188 #gpio-cells = <2>;
189 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */
190 "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
191 "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
192 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
193 };
194
195 i2c-mux@74 { /* u33 */
196 compatible = "nxp,pca9548";
197 #address-cells = <1>;
198 #size-cells = <0>;
199 reg = <0x74>;
200 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
201 pmbus_i2c: i2c@0 {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 reg = <0>;
205 /* On connector J325 */
206 ir38060_41: regulator@41 { /* IR38060 - u259 */
207 compatible = "infineon,ir38060", "infineon,ir38064";
208 reg = <0x41>; /* i2c addr 0x11 */
209 };
210 ir38164_43: regulator@43 { /* IR38164 - u13 */
211 compatible = "infineon,ir38164";
212 reg = <0x43>; /* i2c addr 0x13 */
213 };
214 ir35221_45: pmic@46 { /* IR35221 - u152 */
215 compatible = "infineon,ir35221";
216 reg = <0x46>; /* PMBUS - 0x16 */
217 };
218 irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
219 compatible = "infineon,irps5401";
220 reg = <0x47>; /* i2c addr 0x17 */
221 };
222 ir38164_49: regulator@49 { /* IR38164 - u189 */
223 compatible = "infineon,ir38164";
224 reg = <0x49>; /* i2c addr 0x19 */
225 };
226 irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
227 compatible = "infineon,irps5401";
228 reg = <0x4c>; /* i2c addr 0x1c */
229 };
230 irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
231 compatible = "infineon,irps5401";
232 reg = <0x4d>; /* i2c addr 0x1c */
233 };
234 ir38164_4e: regulator@4e { /* IR38164 - u184 */
235 compatible = "infineon,ir38164";
236 reg = <0x4e>; /* i2c addr 0x1e */
237 };
238 ir38164_4f: regulator@4f { /* IR38164 - u187 */
239 compatible = "infineon,ir38164";
240 reg = <0x4f>; /* i2c addr 0x1f */
241 };
242 };
243 pmbus1_ina226_i2c: i2c@1 {
244 #address-cells = <1>;
245 #size-cells = <0>;
246 reg = <1>;
247 /* FIXME check alerts coming to SC */
248 vccint: ina226@40 { /* u65 */
249 compatible = "ti,ina226";
250 reg = <0x40>;
251 shunt-resistor = <5000>;
252 };
253 vcc_soc: ina226@41 { /* u161 */
254 compatible = "ti,ina226";
255 reg = <0x41>;
256 shunt-resistor = <5000>;
257 };
258 vcc_pmc: ina226@42 { /* u163 */
259 compatible = "ti,ina226";
260 reg = <0x42>;
261 shunt-resistor = <5000>;
262 };
263 vcc_ram: ina226@43 { /* u5 */
264 compatible = "ti,ina226";
265 reg = <0x43>;
266 shunt-resistor = <5000>;
267 };
268 vcc_pslp: ina226@44 { /* u165 */
269 compatible = "ti,ina226";
270 reg = <0x44>;
271 shunt-resistor = <5000>;
272 };
273 vcc_psfp: ina226@45 { /* u164 */
274 compatible = "ti,ina226";
275 reg = <0x45>;
276 shunt-resistor = <5000>;
277 };
278 };
279 i2c@2 { /* NC */ /* FIXME maybe remove */
280 #address-cells = <1>;
281 #size-cells = <0>;
282 reg = <2>;
283 };
284 pmbus2_ina226_i2c: i2c@3 {
285 #address-cells = <1>;
286 #size-cells = <0>;
287 reg = <3>;
288 /* FIXME check alerts coming to SC */
289 vccaux: ina226@40 { /* u166 */
290 compatible = "ti,ina226";
291 reg = <0x40>;
292 shunt-resistor = <5000>;
293 };
294 vccaux_pmc: ina226@41 { /* u168 */
295 compatible = "ti,ina226";
296 reg = <0x41>;
297 shunt-resistor = <5000>;
298 };
299 mgtavcc: ina226@42 { /* u265 */
300 compatible = "ti,ina226";
301 reg = <0x42>;
302 shunt-resistor = <5000>;
303 };
304 vcc1v5: ina226@43 { /* u264 */
305 compatible = "ti,ina226";
306 reg = <0x43>;
307 shunt-resistor = <5000>;
308 };
309 vcco_mio: ina226@45 { /* u172 */
310 compatible = "ti,ina226";
311 reg = <0x45>;
312 shunt-resistor = <5000>;
313 };
314 mgtavtt: ina226@46 { /* u188 */
315 compatible = "ti,ina226";
316 reg = <0x46>;
317 shunt-resistor = <2000>;
318 };
319 vcco_502: ina226@47 { /* u174 */
320 compatible = "ti,ina226";
321 reg = <0x47>;
322 shunt-resistor = <5000>;
323 };
324 mgtvccaux: ina226@48 { /* u176 */
325 compatible = "ti,ina226";
326 reg = <0x48>;
327 shunt-resistor = <5000>;
328 };
329 vcc1v1_lp4: ina226@49 { /* u186 */
330 compatible = "ti,ina226";
331 reg = <0x49>;
332 shunt-resistor = <2000>;
333 };
334 vadj_fmc: ina226@4a { /* u184 */
335 compatible = "ti,ina226";
336 reg = <0x4a>;
337 shunt-resistor = <2000>;
338 };
339 lpdmgtyavcc: ina226@4b { /* u177 */
340 compatible = "ti,ina226";
341 reg = <0x4b>;
342 shunt-resistor = <5000>;
343 };
344 lpdmgtyavtt: ina226@4c { /* u260 */
345 compatible = "ti,ina226";
346 reg = <0x4c>;
347 shunt-resistor = <2000>;
348 };
349 lpdmgtyvccaux: ina226@4d { /* u234 */
350 compatible = "ti,ina226";
351 reg = <0x4d>;
352 shunt-resistor = <5000>;
353 };
354 };
355 i2c@4 { /* NC */
356 #address-cells = <1>;
357 #size-cells = <0>;
358 reg = <4>;
359 };
360 i2c@5 { /* NC */
361 #address-cells = <1>;
362 #size-cells = <0>;
363 reg = <5>;
364 };
365 user_si570: i2c@6 {
366 #address-cells = <1>;
367 #size-cells = <0>;
368 reg = <6>;
369 user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */
370 #clock-cells = <0>;
371 compatible = "silabs,si570";
372 reg = <0x5f>;
373 temperature-stability = <50>;
374 factory-fout = <100000000>;
375 clock-frequency = <100000000>;
376 clock-output-names = "fmc_si570";
377 };
378
379 };
380 /* 7 unused */
381 };
382};
383
384&i2c1 { /* i2c1 MIO 36-37 */
385 status = "okay";
386 clock-frequency = <400000>;
387 pinctrl-names = "default", "gpio";
388 pinctrl-0 = <&pinctrl_i2c1_default>;
389 pinctrl-1 = <&pinctrl_i2c1_gpio>;
390 scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
391 sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
392
393 i2c-mux@74 { /* u35 */
394 compatible = "nxp,pca9548";
395 #address-cells = <1>;
396 #size-cells = <0>;
397 reg = <0x74>;
398 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
399 ref_clk_i2c: i2c@0 {
400 #address-cells = <1>;
401 #size-cells = <0>;
402 reg = <0>;
403 /* Use for storing information about SC board */
404 eeprom: eeprom@54 { /* u34 - m24128 16kB */
405 compatible = "st,24c128", "atmel,24c128";
406 reg = <0x54>; /* & 0x5c */
407 };
408 ref_clk: clock-generator@5d { /* u32 */
409 #clock-cells = <0>;
410 compatible = "silabs,si570";
411 reg = <0x5d>;
412 temperature-stability = <50>;
413 factory-fout = <33333333>;
414 clock-frequency = <33333333>;
415 clock-output-names = "ref_clk";
416 silabs,skip-recall;
417 };
418 };
419 fmcp1_i2c: i2c@1 {
420 #address-cells = <1>;
421 #size-cells = <0>;
422 reg = <1>;
423 /* FIXME connection to Samtec J51C */
424 /* expected eeprom 0x50 SE cards */
425 };
426 i2c@2 { /* NC - FIXME */
427 #address-cells = <1>;
428 #size-cells = <0>;
429 reg = <2>;
430 };
431 lpddr4_si570_clk3_i2c: i2c@3 {
432 #address-cells = <1>;
433 #size-cells = <0>;
434 reg = <3>;
435 lpddr4_clk3: clock-generator@60 { /* u4 */
436 #clock-cells = <0>;
437 compatible = "silabs,si570";
438 reg = <0x60>;
439 temperature-stability = <50>;
440 factory-fout = <200000000>;
441 clock-frequency = <200000000>;
442 clock-output-names = "lpddr4_clk3";
443 };
444 };
445 lpddr4_si570_clk2_i2c: i2c@4 {
446 #address-cells = <1>;
447 #size-cells = <0>;
448 reg = <4>;
449 lpddr4_clk2: clock-generator@60 { /* u3 */
450 #clock-cells = <0>;
451 compatible = "silabs,si570";
452 reg = <0x60>;
453 temperature-stability = <50>;
454 factory-fout = <200000000>;
455 clock-frequency = <200000000>;
456 clock-output-names = "lpddr4_clk2";
457 };
458 };
459 lpddr4_si570_clk1_i2c: i2c@5 {
460 #address-cells = <1>;
461 #size-cells = <0>;
462 reg = <5>;
463 lpddr4_clk1: clock-generator@60 { /* u248 */
464 #clock-cells = <0>;
465 compatible = "silabs,si570";
466 reg = <0x60>;
467 temperature-stability = <50>;
468 factory-fout = <200000000>;
469 clock-frequency = <200000000>;
470 clock-output-names = "lpddr4_clk1";
471 };
472 };
473 qsfpdd_i2c: i2c@6 {
474 #address-cells = <1>;
475 #size-cells = <0>;
476 reg = <6>;
477 /* J1/J2 connectors */
478 };
479 idt8a34001_i2c: i2c@7 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 reg = <7>;
483 /* Via J310 connector */
484 idt_8a34001: phc@5b {
485 compatible = "idt,8a34001"; /* u219B */
486 reg = <0x5b>; /* FIXME not in schematics */
487 };
488 };
489 };
490};
491
492&usb0 { /* MIO52 - MIO63 */
493 status = "okay";
494 phy-names = "usb3-phy";
495 phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
496};
497
498&psgtr {
499 status = "okay";
500 /* sgmii, usb3 */
501 clocks = <&si5332_1>, <&si5332_2>;
502 clock-names = "ref0", "ref1";
503};
504
505&dwc3_0 {
506 status = "okay";
507 dr_mode = "peripheral";
508 snps,dis_u2_susphy_quirk;
509 snps,dis_u3_susphy_quirk;
510 maximum-speed = "super-speed";
511};
512
513&xilinx_ams {
514 status = "okay";
515};
516
517&ams_ps {
518 status = "okay";
519};
520
521&ams_pl {
522 status = "okay";
523};
524
525&pinctrl0 {
526 status = "okay";
527 pinctrl_i2c0_default: i2c0-default {
528 mux {
529 groups = "i2c0_8_grp";
530 function = "i2c0";
531 };
532
533 conf {
534 groups = "i2c0_8_grp";
535 bias-pull-up;
536 slew-rate = <SLEW_RATE_SLOW>;
537 power-source = <IO_STANDARD_LVCMOS18>;
538 };
539 };
540
Michal Simekcf3cd802023-12-19 17:16:50 +0100[diff] [blame]541 pinctrl_i2c0_gpio: i2c0-gpio-grp {
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]542 mux {
543 groups = "gpio0_34_grp", "gpio0_35_grp";
544 function = "gpio0";
545 };
546
547 conf {
548 groups = "gpio0_34_grp", "gpio0_35_grp";
549 slew-rate = <SLEW_RATE_SLOW>;
550 power-source = <IO_STANDARD_LVCMOS18>;
551 };
552 };
553
554 pinctrl_i2c1_default: i2c1-default {
555 mux {
556 groups = "i2c1_9_grp";
557 function = "i2c1";
558 };
559
560 conf {
561 groups = "i2c1_9_grp";
562 bias-pull-up;
563 slew-rate = <SLEW_RATE_SLOW>;
564 power-source = <IO_STANDARD_LVCMOS18>;
565 };
566 };
567
Michal Simekcf3cd802023-12-19 17:16:50 +0100[diff] [blame]568 pinctrl_i2c1_gpio: i2c1-gpio-grp {
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]569 mux {
570 groups = "gpio0_36_grp", "gpio0_37_grp";
571 function = "gpio0";
572 };
573
574 conf {
575 groups = "gpio0_36_grp", "gpio0_37_grp";
576 slew-rate = <SLEW_RATE_SLOW>;
577 power-source = <IO_STANDARD_LVCMOS18>;
578 };
579 };
580};