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git01.mediatek.com / filogic / uboot / 7c326ac86b55e54eaaf98e36a1ead5c19143a009 / . / arch / arm / include / asm / arch-rockchip / cru_rk3128.h
blob: b8565605cd8a6a7e67279c129fe253df463393b7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Kever Yang1650a682017-11-28 16:04:17 +0800[diff] [blame]2/*
3 * Copyright (c) 2017 Rockchip Electronics Co., Ltd
Kever Yang1650a682017-11-28 16:04:17 +0800[diff] [blame]4 */
5
6#ifndef _ASM_ARCH_CRU_RK3128_H
7#define _ASM_ARCH_CRU_RK3128_H
8
9#include <common.h>
10
11#define MHz 1000000
12#define OSC_HZ (24 * MHz)
13
14#define APLL_HZ (600 * MHz)
15#define GPLL_HZ (594 * MHz)
16
17#define CORE_PERI_HZ 150000000
18#define CORE_ACLK_HZ 300000000
19
20#define BUS_ACLK_HZ 148500000
21#define BUS_HCLK_HZ 148500000
22#define BUS_PCLK_HZ 74250000
23
24#define PERI_ACLK_HZ 148500000
25#define PERI_HCLK_HZ 148500000
26#define PERI_PCLK_HZ 74250000
27
28/* Private data for the clock driver - used by rockchip_get_cru() */
29struct rk3128_clk_priv {
30 struct rk3128_cru *cru;
31};
32
33struct rk3128_cru {
34 struct rk3128_pll {
35 unsigned int con0;
36 unsigned int con1;
37 unsigned int con2;
38 unsigned int con3;
39 } pll[4];
40 unsigned int cru_mode_con;
41 unsigned int cru_clksel_con[35];
42 unsigned int cru_clkgate_con[11];
43 unsigned int reserved;
44 unsigned int cru_glb_srst_fst_value;
45 unsigned int cru_glb_srst_snd_value;
46 unsigned int reserved1[2];
47 unsigned int cru_softrst_con[9];
48 unsigned int cru_misc_con;
49 unsigned int reserved2[2];
50 unsigned int cru_glb_cnt_th;
51 unsigned int reserved3[3];
52 unsigned int cru_glb_rst_st;
53 unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
54 unsigned int cru_sdmmc_con[2];
55 unsigned int cru_sdio_con[2];
56 unsigned int reserved5[2];
57 unsigned int cru_emmc_con[2];
58 unsigned int reserved6[4];
59 unsigned int cru_pll_prg_en;
60};
61check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
62
63struct pll_div {
64 u32 refdiv;
65 u32 fbdiv;
66 u32 postdiv1;
67 u32 postdiv2;
68 u32 frac;
69};
70
71enum {
72 /* PLLCON0*/
73 PLL_POSTDIV1_SHIFT = 12,
74 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
75 PLL_FBDIV_SHIFT = 0,
76 PLL_FBDIV_MASK = 0xfff,
77
78 /* PLLCON1 */
79 PLL_RST_SHIFT = 14,
80 PLL_PD_SHIFT = 13,
81 PLL_PD_MASK = 1 << PLL_PD_SHIFT,
82 PLL_DSMPD_SHIFT = 12,
83 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
84 PLL_LOCK_STATUS_SHIFT = 10,
85 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
86 PLL_POSTDIV2_SHIFT = 6,
87 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
88 PLL_REFDIV_SHIFT = 0,
89 PLL_REFDIV_MASK = 0x3f,
90
91 /* CRU_MODE */
92 GPLL_MODE_SHIFT = 12,
93 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
94 GPLL_MODE_SLOW = 0,
95 GPLL_MODE_NORM,
96 GPLL_MODE_DEEP,
97 CPLL_MODE_SHIFT = 8,
98 CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
99 CPLL_MODE_SLOW = 0,
100 CPLL_MODE_NORM,
101 DPLL_MODE_SHIFT = 4,
102 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
103 DPLL_MODE_SLOW = 0,
104 DPLL_MODE_NORM,
105 APLL_MODE_SHIFT = 0,
106 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
107 APLL_MODE_SLOW = 0,
108 APLL_MODE_NORM,
109
110 /* CRU_CLK_SEL0_CON */
111 BUS_ACLK_PLL_SEL_SHIFT = 14,
112 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
113 BUS_ACLK_PLL_SEL_CPLL = 0,
114 BUS_ACLK_PLL_SEL_GPLL,
115 BUS_ACLK_PLL_SEL_GPLL_DIV2,
116 BUS_ACLK_PLL_SEL_GPLL_DIV3,
117 BUS_ACLK_DIV_SHIFT = 8,
118 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
119 CORE_CLK_PLL_SEL_SHIFT = 7,
120 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
121 CORE_CLK_PLL_SEL_APLL = 0,
122 CORE_CLK_PLL_SEL_GPLL_DIV2,
123 CORE_DIV_CON_SHIFT = 0,
124 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
125
126 /* CRU_CLK_SEL1_CON */
127 BUS_PCLK_DIV_SHIFT = 12,
128 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
129 BUS_HCLK_DIV_SHIFT = 8,
130 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
131 CORE_ACLK_DIV_SHIFT = 4,
132 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
133 CORE_PERI_DIV_SHIFT = 0,
134 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
135
136 /* CRU_CLK_SEL2_CON */
137 NANDC_PLL_SEL_SHIFT = 14,
Philipp Tomsichf16060e2017-12-02 00:14:55 +0100[diff] [blame]138 NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT,
Kever Yang1650a682017-11-28 16:04:17 +0800[diff] [blame]139 NANDC_PLL_SEL_CPLL = 0,
140 NANDC_PLL_SEL_GPLL,
141 NANDC_CLK_DIV_SHIFT = 8,
142 NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT,
143 PVTM_CLK_DIV_SHIFT = 0,
144 PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT,
145
146 /* CRU_CLKSEL10_CON */
147 PERI_PLL_SEL_SHIFT = 14,
148 PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT,
149 PERI_PLL_APLL = 0,
150 PERI_PLL_DPLL,
151 PERI_PLL_GPLL,
152 PERI_PCLK_DIV_SHIFT = 12,
153 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
154 PERI_HCLK_DIV_SHIFT = 8,
155 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
156 PERI_ACLK_DIV_SHIFT = 0,
157 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
158
159 /* CRU_CLKSEL11_CON */
160 MMC0_PLL_SHIFT = 6,
161 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
162 MMC0_SEL_APLL = 0,
163 MMC0_SEL_GPLL,
164 MMC0_SEL_GPLL_DIV2,
165 MMC0_SEL_24M,
166 MMC0_DIV_SHIFT = 0,
167 MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
168
169 /* CRU_CLKSEL12_CON */
170 EMMC_PLL_SHIFT = 14,
171 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
172 EMMC_SEL_APLL = 0,
173 EMMC_SEL_GPLL,
174 EMMC_SEL_GPLL_DIV2,
175 EMMC_SEL_24M,
176 EMMC_DIV_SHIFT = 8,
177 EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
178
179 /* CLKSEL_CON24 */
180 SARADC_DIV_CON_SHIFT = 8,
181 SARADC_DIV_CON_MASK = GENMASK(15, 8),
182 SARADC_DIV_CON_WIDTH = 8,
183
184 /* CRU_CLKSEL27_CON*/
185 DCLK_VOP_SEL_SHIFT = 0,
186 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
187 DCLK_VOP_PLL_SEL_CPLL = 0,
188 DCLK_VOP_DIV_CON_SHIFT = 8,
Philipp Tomsich4703ea62017-12-02 00:19:14 +0100[diff] [blame]189 DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT,
Kever Yang1650a682017-11-28 16:04:17 +0800[diff] [blame]190
191 /* CRU_CLKSEL31_CON */
192 VIO0_PLL_SHIFT = 5,
193 VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT,
194 VI00_SEL_CPLL = 0,
195 VIO0_SEL_GPLL,
196 VIO0_DIV_SHIFT = 0,
197 VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT,
198 VIO1_PLL_SHIFT = 13,
199 VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT,
200 VI01_SEL_CPLL = 0,
201 VIO1_SEL_GPLL,
202 VIO1_DIV_SHIFT = 8,
203 VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT,
204
205 /* CRU_SOFTRST5_CON */
206 DDRCTRL_PSRST_SHIFT = 11,
207 DDRCTRL_SRST_SHIFT = 10,
208 DDRPHY_PSRST_SHIFT = 9,
209 DDRPHY_SRST_SHIFT = 8,
210};
211#endif