Haavard Skinnemoen | 7c2842a | 2006-01-20 10:03:53 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2005-2006 Atmel Corporation |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | #ifndef __CPU_AT32AP_ATMEL_MCI_H__ |
| 23 | #define __CPU_AT32AP_ATMEL_MCI_H__ |
| 24 | |
| 25 | /* Atmel MultiMedia Card Interface (MCI) registers */ |
| 26 | #define MMCI_CR 0x0000 |
| 27 | #define MMCI_MR 0x0004 |
| 28 | #define MMCI_DTOR 0x0008 |
| 29 | #define MMCI_SDCR 0x000c |
| 30 | #define MMCI_ARGR 0x0010 |
| 31 | #define MMCI_CMDR 0x0014 |
| 32 | #define MMCI_RSPR 0x0020 |
| 33 | #define MMCI_RSPR1 0x0024 |
| 34 | #define MMCI_RSPR2 0x0028 |
| 35 | #define MMCI_RSPR3 0x002c |
| 36 | #define MMCI_RDR 0x0030 |
| 37 | #define MMCI_TDR 0x0034 |
| 38 | #define MMCI_SR 0x0040 |
| 39 | #define MMCI_IER 0x0044 |
| 40 | #define MMCI_IDR 0x0048 |
| 41 | #define MMCI_IMR 0x004c |
| 42 | |
| 43 | /* Bitfields in CR */ |
| 44 | #define MMCI_MCIEN_OFFSET 0 |
| 45 | #define MMCI_MCIEN_SIZE 1 |
| 46 | #define MMCI_MCIDIS_OFFSET 1 |
| 47 | #define MMCI_MCIDIS_SIZE 1 |
| 48 | #define MMCI_PWSEN_OFFSET 2 |
| 49 | #define MMCI_PWSEN_SIZE 1 |
| 50 | #define MMCI_PWSDIS_OFFSET 3 |
| 51 | #define MMCI_PWSDIS_SIZE 1 |
| 52 | #define MMCI_SWRST_OFFSET 7 |
| 53 | #define MMCI_SWRST_SIZE 1 |
| 54 | |
| 55 | /* Bitfields in MR */ |
| 56 | #define MMCI_CLKDIV_OFFSET 0 |
| 57 | #define MMCI_CLKDIV_SIZE 8 |
| 58 | #define MMCI_PWSDIV_OFFSET 8 |
| 59 | #define MMCI_PWSDIV_SIZE 3 |
| 60 | #define MMCI_PDCPADV_OFFSET 14 |
| 61 | #define MMCI_PDCPADV_SIZE 1 |
| 62 | #define MMCI_PDCMODE_OFFSET 15 |
| 63 | #define MMCI_PDCMODE_SIZE 1 |
| 64 | #define MMCI_BLKLEN_OFFSET 16 |
| 65 | #define MMCI_BLKLEN_SIZE 16 |
| 66 | |
| 67 | /* Bitfields in DTOR */ |
| 68 | #define MMCI_DTOCYC_OFFSET 0 |
| 69 | #define MMCI_DTOCYC_SIZE 4 |
| 70 | #define MMCI_DTOMUL_OFFSET 4 |
| 71 | #define MMCI_DTOMUL_SIZE 3 |
| 72 | |
| 73 | /* Bitfields in SDCR */ |
| 74 | #define MMCI_SCDSEL_OFFSET 0 |
| 75 | #define MMCI_SCDSEL_SIZE 4 |
| 76 | #define MMCI_SCDBUS_OFFSET 7 |
| 77 | #define MMCI_SCDBUS_SIZE 1 |
| 78 | |
| 79 | /* Bitfields in ARGR */ |
| 80 | #define MMCI_ARG_OFFSET 0 |
| 81 | #define MMCI_ARG_SIZE 32 |
| 82 | |
| 83 | /* Bitfields in CMDR */ |
| 84 | #define MMCI_CMDNB_OFFSET 0 |
| 85 | #define MMCI_CMDNB_SIZE 6 |
| 86 | #define MMCI_RSPTYP_OFFSET 6 |
| 87 | #define MMCI_RSPTYP_SIZE 2 |
| 88 | #define MMCI_SPCMD_OFFSET 8 |
| 89 | #define MMCI_SPCMD_SIZE 3 |
| 90 | #define MMCI_OPDCMD_OFFSET 11 |
| 91 | #define MMCI_OPDCMD_SIZE 1 |
| 92 | #define MMCI_MAXLAT_OFFSET 12 |
| 93 | #define MMCI_MAXLAT_SIZE 1 |
| 94 | #define MMCI_TRCMD_OFFSET 16 |
| 95 | #define MMCI_TRCMD_SIZE 2 |
| 96 | #define MMCI_TRDIR_OFFSET 18 |
| 97 | #define MMCI_TRDIR_SIZE 1 |
| 98 | #define MMCI_TRTYP_OFFSET 19 |
| 99 | #define MMCI_TRTYP_SIZE 2 |
| 100 | |
| 101 | /* Bitfields in RSPRx */ |
| 102 | #define MMCI_RSP_OFFSET 0 |
| 103 | #define MMCI_RSP_SIZE 32 |
| 104 | |
| 105 | /* Bitfields in SR/IER/IDR/IMR */ |
| 106 | #define MMCI_CMDRDY_OFFSET 0 |
| 107 | #define MMCI_CMDRDY_SIZE 1 |
| 108 | #define MMCI_RXRDY_OFFSET 1 |
| 109 | #define MMCI_RXRDY_SIZE 1 |
| 110 | #define MMCI_TXRDY_OFFSET 2 |
| 111 | #define MMCI_TXRDY_SIZE 1 |
| 112 | #define MMCI_BLKE_OFFSET 3 |
| 113 | #define MMCI_BLKE_SIZE 1 |
| 114 | #define MMCI_DTIP_OFFSET 4 |
| 115 | #define MMCI_DTIP_SIZE 1 |
| 116 | #define MMCI_NOTBUSY_OFFSET 5 |
| 117 | #define MMCI_NOTBUSY_SIZE 1 |
| 118 | #define MMCI_ENDRX_OFFSET 6 |
| 119 | #define MMCI_ENDRX_SIZE 1 |
| 120 | #define MMCI_ENDTX_OFFSET 7 |
| 121 | #define MMCI_ENDTX_SIZE 1 |
| 122 | #define MMCI_RXBUFF_OFFSET 14 |
| 123 | #define MMCI_RXBUFF_SIZE 1 |
| 124 | #define MMCI_TXBUFE_OFFSET 15 |
| 125 | #define MMCI_TXBUFE_SIZE 1 |
| 126 | #define MMCI_RINDE_OFFSET 16 |
| 127 | #define MMCI_RINDE_SIZE 1 |
| 128 | #define MMCI_RDIRE_OFFSET 17 |
| 129 | #define MMCI_RDIRE_SIZE 1 |
| 130 | #define MMCI_RCRCE_OFFSET 18 |
| 131 | #define MMCI_RCRCE_SIZE 1 |
| 132 | #define MMCI_RENDE_OFFSET 19 |
| 133 | #define MMCI_RENDE_SIZE 1 |
| 134 | #define MMCI_RTOE_OFFSET 20 |
| 135 | #define MMCI_RTOE_SIZE 1 |
| 136 | #define MMCI_DCRCE_OFFSET 21 |
| 137 | #define MMCI_DCRCE_SIZE 1 |
| 138 | #define MMCI_DTOE_OFFSET 22 |
| 139 | #define MMCI_DTOE_SIZE 1 |
| 140 | #define MMCI_OVRE_OFFSET 30 |
| 141 | #define MMCI_OVRE_SIZE 1 |
| 142 | #define MMCI_UNRE_OFFSET 31 |
| 143 | #define MMCI_UNRE_SIZE 1 |
| 144 | |
| 145 | /* Constants for DTOMUL */ |
| 146 | #define MMCI_DTOMUL_1_CYCLE 0 |
| 147 | #define MMCI_DTOMUL_16_CYCLES 1 |
| 148 | #define MMCI_DTOMUL_128_CYCLES 2 |
| 149 | #define MMCI_DTOMUL_256_CYCLES 3 |
| 150 | #define MMCI_DTOMUL_1024_CYCLES 4 |
| 151 | #define MMCI_DTOMUL_4096_CYCLES 5 |
| 152 | #define MMCI_DTOMUL_65536_CYCLES 6 |
| 153 | #define MMCI_DTOMUL_1048576_CYCLES 7 |
| 154 | |
| 155 | /* Constants for RSPTYP */ |
| 156 | #define MMCI_RSPTYP_NO_RESP 0 |
| 157 | #define MMCI_RSPTYP_48_BIT_RESP 1 |
| 158 | #define MMCI_RSPTYP_136_BIT_RESP 2 |
| 159 | |
| 160 | /* Constants for SPCMD */ |
| 161 | #define MMCI_SPCMD_NO_SPEC_CMD 0 |
| 162 | #define MMCI_SPCMD_INIT_CMD 1 |
| 163 | #define MMCI_SPCMD_SYNC_CMD 2 |
| 164 | #define MMCI_SPCMD_INT_CMD 4 |
| 165 | #define MMCI_SPCMD_INT_RESP 5 |
| 166 | |
| 167 | /* Constants for TRCMD */ |
| 168 | #define MMCI_TRCMD_NO_TRANS 0 |
| 169 | #define MMCI_TRCMD_START_TRANS 1 |
| 170 | #define MMCI_TRCMD_STOP_TRANS 2 |
| 171 | |
| 172 | /* Constants for TRTYP */ |
| 173 | #define MMCI_TRTYP_BLOCK 0 |
| 174 | #define MMCI_TRTYP_MULTI_BLOCK 1 |
| 175 | #define MMCI_TRTYP_STREAM 2 |
| 176 | |
| 177 | /* Bit manipulation macros */ |
| 178 | #define MMCI_BIT(name) \ |
| 179 | (1 << MMCI_##name##_OFFSET) |
| 180 | #define MMCI_BF(name,value) \ |
| 181 | (((value) & ((1 << MMCI_##name##_SIZE) - 1)) \ |
| 182 | << MMCI_##name##_OFFSET) |
| 183 | #define MMCI_BFEXT(name,value) \ |
| 184 | (((value) >> MMCI_##name##_OFFSET)\ |
| 185 | & ((1 << MMCI_##name##_SIZE) - 1)) |
| 186 | #define MMCI_BFINS(name,value,old) \ |
| 187 | (((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \ |
| 188 | << MMCI_##name##_OFFSET)) \ |
| 189 | | MMCI_BF(name,value)) |
| 190 | |
| 191 | /* Register access macros */ |
| 192 | #define mmci_readl(reg) \ |
| 193 | readl((void *)MMCI_BASE + MMCI_##reg) |
| 194 | #define mmci_writel(reg,value) \ |
| 195 | writel((value), (void *)MMCI_BASE + MMCI_##reg) |
| 196 | |
| 197 | #endif /* __CPU_AT32AP_ATMEL_MCI_H__ */ |