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git01.mediatek.com / filogic / uboot / 7c20aef3f4f288a949cfba053b0944f78ea655ef / . / drivers / pci / pci_sh7751.c
blob: a058e1d37fc69285f3c238a2862b450b8aeda342 [file] [log] [blame]
Nobuhiro Iwamatsu7d180fd2008-03-24 01:53:01 +0900[diff] [blame]1/*
2 * SH7751 PCI Controller (PCIC) for U-Boot.
3 * (C) Dustin McIntire (dustin@sensoria.com)
4 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/processor.h>
27#include <asm/io.h>
28#include <pci.h>
29
30/* Register addresses and such */
31#define SH7751_BCR1 (vu_long *)0xFF800000
32#define SH7751_BCR2 (vu_short*)0xFF800004
33#define SH7751_WCR1 (vu_long *)0xFF800008
34#define SH7751_WCR2 (vu_long *)0xFF80000C
35#define SH7751_WCR3 (vu_long *)0xFF800010
36#define SH7751_MCR (vu_long *)0xFF800014
37#define SH7751_BCR3 (vu_short*)0xFF800050
38#define SH7751_PCICONF0 (vu_long *)0xFE200000
39#define SH7751_PCICONF1 (vu_long *)0xFE200004
40#define SH7751_PCICONF2 (vu_long *)0xFE200008
41#define SH7751_PCICONF3 (vu_long *)0xFE20000C
42#define SH7751_PCICONF4 (vu_long *)0xFE200010
43#define SH7751_PCICONF5 (vu_long *)0xFE200014
44#define SH7751_PCICONF6 (vu_long *)0xFE200018
45#define SH7751_PCICR (vu_long *)0xFE200100
46#define SH7751_PCILSR0 (vu_long *)0xFE200104
47#define SH7751_PCILSR1 (vu_long *)0xFE200108
48#define SH7751_PCILAR0 (vu_long *)0xFE20010C
49#define SH7751_PCILAR1 (vu_long *)0xFE200110
50#define SH7751_PCIMBR (vu_long *)0xFE2001C4
51#define SH7751_PCIIOBR (vu_long *)0xFE2001C8
52#define SH7751_PCIPINT (vu_long *)0xFE2001CC
53#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
54#define SH7751_PCICLKR (vu_long *)0xFE2001D4
55#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
56#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
57#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
58#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
59#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
60#define SH7751_PCIMCR (vu_long *)0xFE2001F4
61#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
62
63#define BCR1_BREQEN 0x00080000
64#define PCI_SH7751_ID 0x35051054
65#define PCI_SH7751R_ID 0x350E1054
66#define SH7751_PCICONF1_WCC 0x00000080
67#define SH7751_PCICONF1_PER 0x00000040
68#define SH7751_PCICONF1_BUM 0x00000004
69#define SH7751_PCICONF1_MES 0x00000002
70#define SH7751_PCICONF1_CMDS 0x000000C6
71#define SH7751_PCI_HOST_BRIDGE 0x6
72#define SH7751_PCICR_PREFIX 0xa5000000
73#define SH7751_PCICR_PRST 0x00000002
74#define SH7751_PCICR_CFIN 0x00000001
75#define SH7751_PCIPINT_D3 0x00000002
76#define SH7751_PCIPINT_D0 0x00000001
77#define SH7751_PCICLKR_PREFIX 0xa5000000
78
79#define SH7751_PCI_MEM_BASE 0xFD000000
80#define SH7751_PCI_MEM_SIZE 0x01000000
81#define SH7751_PCI_IO_BASE 0xFE240000
82#define SH7751_PCI_IO_SIZE 0x00040000
83
84#define SH7751_CS3_BASE_ADDR 0x0C000000
85#define SH7751_P2CS3_BASE_ADDR 0xAC000000
86
87#define SH7751_PCIPAR (vu_long *)0xFE2001C0
88#define SH7751_PCIPDR (vu_long *)0xFE200220
89
90#define p4_in(addr) *(addr)
91#define p4_out(data,addr) *(addr) = (data)
92
93/* Double word */
94int pci_sh4_read_config_dword(struct pci_controller *hose,
95 pci_dev_t dev, int offset, u32 * value)
96{
97 u32 par_data = 0x80000000 | dev;
98
99 p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
100 *value = p4_in(SH7751_PCIPDR);
101
102 return 0;
103}
104
105int pci_sh4_write_config_dword(struct pci_controller *hose,
106 pci_dev_t dev, int offset, u32 * value)
107{
108 u32 par_data = 0x80000000 | dev;
109
110 p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
111 p4_out(value, SH7751_PCIPDR);
112
113 return 0;
114}
115
116int pci_sh7751_init(struct pci_controller *hose)
117{
118 /* Double-check that we're a 7751 or 7751R chip */
119 if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
120 && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
121 printf("PCI: Unknown PCI host bridge.\n");
122 return 1;
123 }
124 printf("PCI: SH7751 PCI host bridge found.\n");
125
126 /* Double-check some BSC config settings */
127 /* (Area 3 non-MPX 32-bit, PCI bus pins) */
128 if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
129 printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1));
130 return 2;
131 }
132 if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
133 printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
134 return 3;
135 }
136 if (p4_in(SH7751_BCR2) & 0x01) {
137 printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
138 return 4;
139 }
140
141 /* Force BREQEN in BCR1 to allow PCIC access */
142 p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
143
144 /* Toggle PCI reset pin */
145 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
146 udelay(32);
147 p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
148
149 /* Set cmd bits: WCC, PER, BUM, MES */
150 /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
151 p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
152
153 /* Define this host as the host bridge */
154 p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
155
156 /* Force PCI clock(s) on */
157 p4_out(0, SH7751_PCICLKR);
158 p4_out(0x03, SH7751_PCICLKR);
159
160 /* Clear powerdown IRQs, also mask them (unused) */
161 p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
162 p4_out(0, SH7751_PCIPINTM);
163
164 p4_out(0xab000001, SH7751_PCICONF4);
165
166 /* Set up target memory mappings (for external DMA access) */
167 /* Map both P0 and P2 range to Area 3 RAM for ease of use */
168 p4_out((64 - 1) << 20, SH7751_PCILSR0);
169 p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0);
170 p4_out(0, SH7751_PCILSR1);
171 p4_out(0, SH7751_PCILAR1);
172 p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5);
173 p4_out(0xd0000000, SH7751_PCICONF6);
174
175 /* Map memory window to same address on PCI bus */
176 p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
177
178 /* Map IO window to same address on PCI bus */
179 p4_out(0x2000 & 0xfffc0000, SH7751_PCIIOBR);
180
181 /* set BREQEN */
182 p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
183
184 /* Copy BSC registers into PCI BSC */
185 p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
186 p4_out(inl(SH7751_BCR2), SH7751_PCIBCR2);
187 p4_out(inl(SH7751_BCR3), SH7751_PCIBCR3);
188 p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
189 p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
190 p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
191 p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
192
193 /* Finally, set central function init complete */
194 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
195
196 pci_sh4_init(hose);
197
198 return 0;
199}