| Svyatoslav Ryhel | fcb1d91 | 2023-06-30 10:29:05 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * T30 LGE X3 SPL stage configuration |
| 4 | * |
| 5 | * (C) Copyright 2010-2013 |
| 6 | * NVIDIA Corporation <www.nvidia.com> |
| 7 | * |
| 8 | * (C) Copyright 2022 |
| 9 | * Svyatoslav Ryhel <clamor95@gmail.com> |
| 10 | */ |
| 11 | |
| 12 | #include <common.h> |
| 13 | #include <asm/arch-tegra/tegra_i2c.h> |
| 14 | #include <linux/delay.h> |
| 15 | |
| 16 | #define MAX77663_I2C_ADDR (0x1C << 1) |
| 17 | |
| 18 | #define MAX77663_REG_SD0 0x16 |
| 19 | #define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0) |
| 20 | #define MAX77663_REG_SD1 0x17 |
| 21 | #define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1) |
| 22 | #define MAX77663_REG_LDO4 0x2B |
| 23 | #define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4) |
| 24 | |
| 25 | #define MAX77663_REG_GPIO1 0x37 |
| 26 | #define MAX77663_REG_GPIO1_DATA (0x0800 | MAX77663_REG_GPIO1) |
| 27 | #define MAX77663_REG_GPIO4 0x3A |
| 28 | #define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4) |
| 29 | |
| 30 | void pmic_enable_cpu_vdd(void) |
| 31 | { |
| 32 | /* Set VDD_CORE to 1.200V. */ |
| 33 | tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA); |
| 34 | |
| 35 | udelay(1000); |
| 36 | |
| 37 | /* Bring up VDD_CPU to 1.0125V. */ |
| 38 | tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA); |
| 39 | udelay(1000); |
| 40 | |
| 41 | /* Bring up VDD_RTC to 1.200V. */ |
| 42 | tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA); |
| 43 | udelay(10 * 1000); |
| 44 | |
| 45 | /* Set GPIO4 and GPIO1 states */ |
| 46 | tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA); |
| 47 | tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO1_DATA); |
| 48 | } |