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git01.mediatek.com / filogic / uboot / 7bf2f8cabbd5ac8f8e4ed35e32d010ca2fd1856c / . / drivers / pinctrl / mediatek / pinctrl-mt7988.c
blob: 03a38e83dfa6f31ef195f4e41eb30a473c4ad513 [file] [log] [blame]
developer7815b2b2023-07-19 17:16:50 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7#include <dm.h>
8#include "pinctrl-mtk-common.h"
9
10enum MT7988_PINCTRL_REG_PAGE {
11 GPIO_BASE,
12 IOCFG_TR_BASE,
13 IOCFG_BR_BASE,
14 IOCFG_RB_BASE,
15 IOCFG_LB_BASE,
16 IOCFG_TL_BASE,
17};
18
19#define MT7988_TYPE0_PIN(_number, _name) \
20 MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
21
22#define MT7988_TYPE1_PIN(_number, _name) \
23 MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
24
25#define MT7988_TYPE2_PIN(_number, _name) \
26 MTK_TYPED_PIN(_number, _name, DRV_FIXED, IO_TYPE_GRP2)
27
28#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
29 PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \
30 _s_bit, _x_bits, 32, 0)
31
32#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
33 _x_bits) \
34 PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
35 _s_bit, _x_bits, 32, 0)
36
37#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
38 _x_bits) \
39 PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
40 _s_bit, _x_bits, 32, 1)
41
42static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
43 PIN_FIELD_GPIO(0, 83, 0x300, 0x10, 0, 4),
44};
45
46static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
47 PIN_FIELD_GPIO(0, 83, 0x0, 0x10, 0, 1),
48};
49
50static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
51 PIN_FIELD_GPIO(0, 83, 0x200, 0x10, 0, 1),
52};
53
54static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
55 PIN_FIELD_GPIO(0, 83, 0x100, 0x10, 0, 1),
56};
57
58static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
59 PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x30, 0x10, 13, 1),
60 PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
61 PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x30, 0x10, 11, 1),
62 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
63 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
64 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
65 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
66
67 PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x30, 0x10, 8, 1),
68 PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x30, 0x10, 6, 1),
69 PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x30, 0x10, 5, 1),
70 PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x30, 0x10, 3, 1),
71
72 PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
73 PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x40, 0x10, 21, 1),
74 PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
75 PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
76
77 PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
78 PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
79 PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
80 PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
81
82 PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x30, 0x10, 7, 1),
83 PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x30, 0x10, 4, 1),
84
85 PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x50, 0x10, 17, 1),
86 PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x50, 0x10, 23, 1),
87 PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x50, 0x10, 20, 1),
88 PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x50, 0x10, 19, 1),
89 PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x50, 0x10, 21, 1),
90 PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x50, 0x10, 22, 1),
91 PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x50, 0x10, 18, 1),
92 PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x50, 0x10, 25, 1),
93 PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x50, 0x10, 26, 1),
94 PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x50, 0x10, 27, 1),
95 PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x50, 0x10, 24, 1),
96 PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x50, 0x10, 28, 1),
97 PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
98 PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x50, 0x10, 31, 1),
99 PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x50, 0x10, 29, 1),
100 PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x50, 0x10, 30, 1),
101 PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x60, 0x10, 1, 1),
102 PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x50, 0x10, 11, 1),
103 PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x50, 0x10, 10, 1),
104 PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x50, 0x10, 0, 1),
105 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x50, 0x10, 1, 1),
106 PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x50, 0x10, 9, 1),
107 PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x50, 0x10, 8, 1),
108 PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x50, 0x10, 7, 1),
109 PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x50, 0x10, 6, 1),
110 PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x50, 0x10, 5, 1),
111 PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x50, 0x10, 4, 1),
112 PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x50, 0x10, 3, 1),
113 PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x50, 0x10, 2, 1),
114 PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x50, 0x10, 15, 1),
115 PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x50, 0x10, 12, 1),
116 PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x50, 0x10, 13, 1),
117 PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x50, 0x10, 14, 1),
118 PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x50, 0x10, 16, 1),
119
120 PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
121 PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x40, 0x10, 15, 1),
122 PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x40, 0x10, 13, 1),
123 PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
124 PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
125 PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
126 PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x40, 0x10, 3, 1),
127 PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x40, 0x10, 7, 1),
128 PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x40, 0x10, 20, 1),
129 PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x40, 0x10, 8, 1),
130 PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
131 PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x40, 0x10, 10, 1),
132 PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x40, 0x10, 11, 1),
133 PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x40, 0x10, 12, 1),
134
135 PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
136 PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
137 PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
138 PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
139
140 PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x30, 0x10, 10, 1),
141 PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x30, 0x10, 1, 1),
142 PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x30, 0x10, 11, 1),
143 PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x30, 0x10, 9, 1),
144 PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x30, 0x10, 2, 1),
145 PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x30, 0x10, 0, 1),
146 PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x30, 0x10, 12, 1),
147
148 PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 18, 1),
149 PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 19, 1),
150 PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
151 PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 17, 1),
152};
153
154static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
155 PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0xc0, 0x10, 13, 1),
156 PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0xc0, 0x10, 14, 1),
157 PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0xc0, 0x10, 11, 1),
158 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0xc0, 0x10, 12, 1),
159 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0xc0, 0x10, 0, 1),
160 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0xc0, 0x10, 9, 1),
161 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0xc0, 0x10, 10, 1),
162
163 PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0xb0, 0x10, 8, 1),
164 PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0xb0, 0x10, 6, 1),
165 PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0xb0, 0x10, 5, 1),
166 PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0xb0, 0x10, 3, 1),
167
168 PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0xe0, 0x10, 0, 1),
169 PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0xe0, 0x10, 21, 1),
170 PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0xe0, 0x10, 1, 1),
171 PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0xe0, 0x10, 2, 1),
172
173 PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0xc0, 0x10, 7, 1),
174 PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0xc0, 0x10, 8, 1),
175 PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0xc0, 0x10, 3, 1),
176 PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0xc0, 0x10, 4, 1),
177
178 PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0xb0, 0x10, 7, 1),
179 PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0xb0, 0x10, 4, 1),
180
181 PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x140, 0x10, 17, 1),
182 PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x140, 0x10, 23, 1),
183 PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x140, 0x10, 20, 1),
184 PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x140, 0x10, 19, 1),
185 PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x140, 0x10, 21, 1),
186 PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x140, 0x10, 22, 1),
187 PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x140, 0x10, 18, 1),
188 PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x140, 0x10, 25, 1),
189 PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x140, 0x10, 26, 1),
190 PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x140, 0x10, 27, 1),
191 PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x140, 0x10, 24, 1),
192 PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x140, 0x10, 28, 1),
193 PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x150, 0x10, 0, 1),
194 PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x140, 0x10, 31, 1),
195 PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x140, 0x10, 29, 1),
196 PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x140, 0x10, 30, 1),
197 PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x150, 0x10, 1, 1),
198 PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x140, 0x10, 11, 1),
199 PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x140, 0x10, 10, 1),
200 PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x140, 0x10, 0, 1),
201 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x140, 0x10, 1, 1),
202 PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x140, 0x10, 9, 1),
203 PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x140, 0x10, 8, 1),
204 PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x140, 0x10, 7, 1),
205 PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x140, 0x10, 6, 1),
206 PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x140, 0x10, 5, 1),
207 PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x140, 0x10, 4, 1),
208 PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x140, 0x10, 3, 1),
209 PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x140, 0x10, 2, 1),
210 PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x140, 0x10, 15, 1),
211 PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x140, 0x10, 12, 1),
212 PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x140, 0x10, 13, 1),
213 PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x140, 0x10, 14, 1),
214 PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x140, 0x10, 16, 1),
215
216 PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0xe0, 0x10, 14, 1),
217 PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0xe0, 0x10, 15, 1),
218 PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0xe0, 0x10, 13, 1),
219 PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0xe0, 0x10, 4, 1),
220 PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0xe0, 0x10, 5, 1),
221 PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0xe0, 0x10, 6, 1),
222 PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0xe0, 0x10, 3, 1),
223 PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0xe0, 0x10, 7, 1),
224 PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0xe0, 0x10, 20, 1),
225 PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0xe0, 0x10, 8, 1),
226 PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0xe0, 0x10, 9, 1),
227 PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0xe0, 0x10, 10, 1),
228 PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0xe0, 0x10, 11, 1),
229 PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0xe0, 0x10, 12, 1),
230
231 PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0xc0, 0x10, 1, 1),
232 PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0xc0, 0x10, 2, 1),
233 PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0xc0, 0x10, 5, 1),
234 PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0xc0, 0x10, 6, 1),
235
236 PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0xb0, 0x10, 10, 1),
237 PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0xb0, 0x10, 1, 1),
238 PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0xb0, 0x10, 11, 1),
239 PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0xb0, 0x10, 9, 1),
240 PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0xb0, 0x10, 2, 1),
241 PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0xb0, 0x10, 0, 1),
242 PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0xb0, 0x10, 12, 1),
243
244 PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0xe0, 0x10, 18, 1),
245 PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0xe0, 0x10, 19, 1),
246 PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0xe0, 0x10, 16, 1),
247 PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0xe0, 0x10, 17, 1),
248};
249
250static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
251 PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x60, 0x10, 5, 1),
252 PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
253 PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
254 PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
255
256 PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x70, 0x10, 0, 1),
257 PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x70, 0x10, 1, 1),
258 PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x70, 0x10, 2, 1),
259
260 PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x60, 0x10, 7, 1),
261 PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x60, 0x10, 6, 1),
262 PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
263 PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
264 PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x60, 0x10, 8, 1),
265};
266
267static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
268 PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x40, 0x10, 5, 1),
269 PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
270 PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
271 PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
272
273 PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
274 PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
275
276 PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
277 PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x40, 0x10, 5, 1),
278 PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
279 PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
280
281 PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
282 PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
283 PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x40, 0x10, 3, 1),
284
285 PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x40, 0x10, 7, 1),
286 PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x40, 0x10, 6, 1),
287 PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
288 PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
289 PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x40, 0x10, 8, 1),
290};
291
292static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
293 PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x00, 0x10, 21, 3),
294 PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
295 PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x00, 0x10, 15, 3),
296 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x00, 0x10, 18, 3),
297 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
298 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x00, 0x10, 9, 3),
299 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
300
301 PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x00, 0x10, 24, 3),
302 PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x00, 0x10, 28, 3),
303 PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x00, 0x10, 15, 3),
304 PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x00, 0x10, 9, 3),
305
306 PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
307 PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x20, 0x10, 3, 3),
308 PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
309 PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
310
311 PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x00, 0x10, 21, 3),
312 PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x00, 0x10, 12, 3),
313
314 PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
315 PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
316 PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
317 PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
318 PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
319 PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x20, 0x10, 6, 3),
320 PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x10, 0x10, 24, 3),
321 PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
322 PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x20, 0x10, 18, 3),
323 PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
324 PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x20, 0x10, 12, 3),
325 PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x20, 0x10, 24, 3),
326 PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x30, 0x10, 6, 3),
327 PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x30, 0x10, 3, 3),
328 PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x20, 0x10, 27, 3),
329 PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x30, 0x10, 0, 3),
330 PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x30, 0x10, 9, 3),
331 PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x10, 0x10, 3, 3),
332 PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
333 PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
334 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
335 PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x00, 0x10, 27, 3),
336 PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
337 PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
338 PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x00, 0x10, 18, 3),
339 PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x00, 0x10, 15, 3),
340 PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x00, 0x10, 12, 3),
341 PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x00, 0x10, 9, 3),
342 PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x00, 0x10, 6, 3),
343 PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
344 PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
345 PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
346 PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
347 PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
348
349 PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
350 PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x10, 0x10, 15, 3),
351 PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x10, 0x10, 9, 3),
352 PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
353 PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
354 PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x00, 0x10, 18, 3),
355 PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x00, 0x10, 9, 3),
356 PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x00, 0x10, 21, 3),
357 PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x20, 0x10, 0, 3),
358 PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x00, 0x10, 24, 3),
359 PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
360 PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
361 PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x10, 0x10, 3, 3),
362 PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x10, 0x10, 6, 3),
363
364 PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
365 PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
366
367 PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x10, 0x10, 0, 3),
368 PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x00, 0x10, 3, 3),
369 PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x10, 0x10, 3, 3),
370 PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x00, 0x10, 27, 3),
371 PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x00, 0x10, 6, 3),
372 PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x00, 0x10, 0, 3),
373 PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x10, 0x10, 6, 3),
374
375 PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x10, 0x10, 24, 3),
376 PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 27, 3),
377 PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
378 PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 21, 3),
379};
380
381static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
382 PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x50, 0x10, 7, 1),
383 PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
384 PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x50, 0x10, 5, 1),
385 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 6, 1),
386 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
387 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1),
388 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
389
390 PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x60, 0x10, 0, 1),
391 PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x60, 0x10, 18, 1),
392
393 PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
394 PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x50, 0x10, 1, 1),
395
396 PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
397 PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
398 PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x70, 0x10, 20, 1),
399 PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x70, 0x10, 19, 1),
400 PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
401 PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x70, 0x10, 22, 1),
402 PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
403 PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
404 PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x70, 0x10, 26, 1),
405 PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
406 PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x70, 0x10, 24, 1),
407 PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x70, 0x10, 28, 1),
408 PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
409 PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x70, 0x10, 31, 1),
410 PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x70, 0x10, 29, 1),
411 PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x70, 0x10, 30, 1),
412 PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x80, 0x10, 1, 1),
413 PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x70, 0x10, 11, 1),
414 PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 10, 1),
415 PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
416 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
417 PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 9, 1),
418 PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
419 PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 7, 1),
420 PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 6, 1),
421 PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 5, 1),
422 PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
423 PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
424 PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
425 PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
426 PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
427 PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
428 PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
429 PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
430
431 PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x60, 0x10, 12, 1),
432 PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x60, 0x10, 13, 1),
433 PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x60, 0x10, 11, 1),
434 PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x60, 0x10, 2, 1),
435 PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x60, 0x10, 3, 1),
436 PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x60, 0x10, 4, 1),
437 PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x60, 0x10, 1, 1),
438 PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x60, 0x10, 5, 1),
439 PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x60, 0x10, 6, 1),
440 PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x60, 0x10, 7, 1),
441 PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x60, 0x10, 8, 1),
442 PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x60, 0x10, 9, 1),
443 PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x60, 0x10, 10, 1),
444
445 PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
446 PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
447
448 PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x50, 0x10, 3, 1),
449 PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
450
451 PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x60, 0x10, 16, 1),
452 PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x60, 0x10, 17, 1),
453 PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x60, 0x10, 14, 1),
454 PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x60, 0x10, 15, 1),
455};
456
457static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
458 PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x60, 0x10, 7, 1),
459 PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x60, 0x10, 8, 1),
460 PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x60, 0x10, 5, 1),
461 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x60, 0x10, 6, 1),
462 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x60, 0x10, 0, 1),
463 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x60, 0x10, 3, 1),
464 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x60, 0x10, 4, 1),
465
466 PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
467 PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x80, 0x10, 18, 1),
468
469 PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x70, 0x10, 2, 1),
470 PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x70, 0x10, 1, 1),
471
472 PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x90, 0x10, 17, 1),
473 PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x90, 0x10, 23, 1),
474 PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x90, 0x10, 20, 1),
475 PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x90, 0x10, 19, 1),
476 PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x90, 0x10, 21, 1),
477 PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x90, 0x10, 22, 1),
478 PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x90, 0x10, 18, 1),
479 PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x90, 0x10, 25, 1),
480 PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x90, 0x10, 26, 1),
481 PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x90, 0x10, 27, 1),
482 PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x90, 0x10, 24, 1),
483 PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x90, 0x10, 28, 1),
484 PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xa0, 0x10, 0, 1),
485 PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x90, 0x10, 31, 1),
486 PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x90, 0x10, 29, 1),
487 PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x90, 0x10, 30, 1),
488 PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xa0, 0x10, 1, 1),
489 PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x90, 0x10, 11, 1),
490 PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x90, 0x10, 10, 1),
491 PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x90, 0x10, 0, 1),
492 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x90, 0x10, 1, 1),
493 PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x90, 0x10, 9, 1),
494 PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x90, 0x10, 8, 1),
495 PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x90, 0x10, 7, 1),
496 PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x90, 0x10, 6, 1),
497 PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x90, 0x10, 5, 1),
498 PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x90, 0x10, 4, 1),
499 PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x90, 0x10, 3, 1),
500 PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x90, 0x10, 2, 1),
501 PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x90, 0x10, 15, 1),
502 PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x90, 0x10, 12, 1),
503 PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x90, 0x10, 13, 1),
504 PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x90, 0x10, 14, 1),
505 PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x90, 0x10, 16, 1),
506
507 PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x80, 0x10, 12, 1),
508 PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x80, 0x10, 13, 1),
509 PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x80, 0x10, 11, 1),
510 PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
511 PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x80, 0x10, 3, 1),
512 PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
513 PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
514 PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
515 PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
516 PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x80, 0x10, 7, 1),
517 PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x80, 0x10, 8, 1),
518 PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
519 PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x80, 0x10, 10, 1),
520
521 PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x60, 0x10, 1, 1),
522 PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x60, 0x10, 2, 1),
523
524 PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x70, 0x10, 3, 1),
525 PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x70, 0x10, 0, 1),
526
527 PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
528 PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 17, 1),
529 PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
530 PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 15, 1),
531};
532
533static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
534 PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x70, 0x10, 7, 1),
535 PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
536 PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x70, 0x10, 5, 1),
537 PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x70, 0x10, 6, 1),
538 PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
539 PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x70, 0x10, 3, 1),
540 PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
541
542 PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x90, 0x10, 0, 1),
543 PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x90, 0x10, 18, 1),
544
545 PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x80, 0x10, 2, 1),
546 PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x80, 0x10, 1, 1),
547
548 PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0xb0, 0x10, 17, 1),
549 PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0xb0, 0x10, 23, 1),
550 PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0xb0, 0x10, 20, 1),
551 PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0xb0, 0x10, 19, 1),
552 PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0xb0, 0x10, 21, 1),
553 PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0xb0, 0x10, 22, 1),
554 PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0xb0, 0x10, 18, 1),
555 PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0xb0, 0x10, 25, 1),
556 PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0xb0, 0x10, 26, 1),
557 PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0xb0, 0x10, 27, 1),
558 PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0xb0, 0x10, 24, 1),
559 PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0xb0, 0x10, 28, 1),
560 PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xc0, 0x10, 0, 1),
561 PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0xb0, 0x10, 31, 1),
562 PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0xb0, 0x10, 29, 1),
563 PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0xb0, 0x10, 30, 1),
564 PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xc0, 0x10, 1, 1),
565 PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0xb0, 0x10, 11, 1),
566 PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xb0, 0x10, 10, 1),
567 PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xb0, 0x10, 0, 1),
568 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xb0, 0x10, 1, 1),
569 PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xb0, 0x10, 9, 1),
570 PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xb0, 0x10, 8, 1),
571 PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xb0, 0x10, 7, 1),
572 PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xb0, 0x10, 6, 1),
573 PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xb0, 0x10, 5, 1),
574 PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xb0, 0x10, 4, 1),
575 PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xb0, 0x10, 3, 1),
576 PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xb0, 0x10, 2, 1),
577 PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0xb0, 0x10, 15, 1),
578 PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0xb0, 0x10, 12, 1),
579 PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0xb0, 0x10, 13, 1),
580 PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0xb0, 0x10, 14, 1),
581 PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0xb0, 0x10, 16, 1),
582
583 PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x90, 0x10, 12, 1),
584 PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x90, 0x10, 13, 1),
585 PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x90, 0x10, 11, 1),
586 PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x90, 0x10, 2, 1),
587 PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x90, 0x10, 3, 1),
588 PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x90, 0x10, 4, 1),
589 PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x90, 0x10, 1, 1),
590 PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x90, 0x10, 5, 1),
591 PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x90, 0x10, 6, 1),
592 PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x90, 0x10, 7, 1),
593 PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x90, 0x10, 8, 1),
594 PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x90, 0x10, 9, 1),
595 PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x90, 0x10, 10, 1),
596
597 PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
598 PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
599
600 PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x80, 0x10, 3, 1),
601 PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x80, 0x10, 0, 1),
602
603 PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x90, 0x10, 16, 1),
604 PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x90, 0x10, 17, 1),
605 PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x90, 0x10, 14, 1),
606 PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1),
607};
608
609static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
610 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
611 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
612 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
613 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
614 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
615 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
616 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
617 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
618 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
619 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
620 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
621 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
622};
623
624static const struct mtk_pin_desc mt7988_pins[] = {
625 MT7988_TYPE0_PIN(0, "UART2_RXD"),
626 MT7988_TYPE0_PIN(1, "UART2_TXD"),
627 MT7988_TYPE0_PIN(2, "UART2_CTS"),
628 MT7988_TYPE0_PIN(3, "UART2_RTS"),
629 MT7988_TYPE0_PIN(4, "GPIO_A"),
630 MT7988_TYPE0_PIN(5, "SMI_0_MDC"),
631 MT7988_TYPE0_PIN(6, "SMI_0_MDIO"),
632 MT7988_TYPE1_PIN(7, "PCIE30_2L_0_WAKE_N"),
633 MT7988_TYPE1_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
634 MT7988_TYPE1_PIN(9, "PCIE30_1L_1_WAKE_N"),
635 MT7988_TYPE1_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
636 MT7988_TYPE0_PIN(11, "GPIO_P"),
637 MT7988_TYPE0_PIN(12, "WATCHDOG"),
638 MT7988_TYPE1_PIN(13, "GPIO_RESET"),
639 MT7988_TYPE1_PIN(14, "GPIO_WPS"),
640 MT7988_TYPE2_PIN(15, "PMIC_I2C_SCL"),
641 MT7988_TYPE2_PIN(16, "PMIC_I2C_SDA"),
642 MT7988_TYPE2_PIN(17, "I2C_1_SCL"),
643 MT7988_TYPE2_PIN(18, "I2C_1_SDA"),
644 MT7988_TYPE0_PIN(19, "PCIE30_2L_0_PRESET_N"),
645 MT7988_TYPE0_PIN(20, "PCIE30_1L_1_PRESET_N"),
646 MT7988_TYPE0_PIN(21, "PWMD1"),
647 MT7988_TYPE0_PIN(22, "SPI0_WP"),
648 MT7988_TYPE0_PIN(23, "SPI0_HOLD"),
649 MT7988_TYPE0_PIN(24, "SPI0_CSB"),
650 MT7988_TYPE0_PIN(25, "SPI0_MISO"),
651 MT7988_TYPE0_PIN(26, "SPI0_MOSI"),
652 MT7988_TYPE0_PIN(27, "SPI0_CLK"),
653 MT7988_TYPE0_PIN(28, "SPI1_CSB"),
654 MT7988_TYPE0_PIN(29, "SPI1_MISO"),
655 MT7988_TYPE0_PIN(30, "SPI1_MOSI"),
656 MT7988_TYPE0_PIN(31, "SPI1_CLK"),
657 MT7988_TYPE0_PIN(32, "SPI2_CLK"),
658 MT7988_TYPE0_PIN(33, "SPI2_MOSI"),
659 MT7988_TYPE0_PIN(34, "SPI2_MISO"),
660 MT7988_TYPE0_PIN(35, "SPI2_CSB"),
661 MT7988_TYPE0_PIN(36, "SPI2_HOLD"),
662 MT7988_TYPE0_PIN(37, "SPI2_WP"),
663 MT7988_TYPE0_PIN(38, "EMMC_RSTB"),
664 MT7988_TYPE0_PIN(39, "EMMC_DSL"),
665 MT7988_TYPE0_PIN(40, "EMMC_CK"),
666 MT7988_TYPE0_PIN(41, "EMMC_CMD"),
667 MT7988_TYPE0_PIN(42, "EMMC_DATA_7"),
668 MT7988_TYPE0_PIN(43, "EMMC_DATA_6"),
669 MT7988_TYPE0_PIN(44, "EMMC_DATA_5"),
670 MT7988_TYPE0_PIN(45, "EMMC_DATA_4"),
671 MT7988_TYPE0_PIN(46, "EMMC_DATA_3"),
672 MT7988_TYPE0_PIN(47, "EMMC_DATA_2"),
673 MT7988_TYPE0_PIN(48, "EMMC_DATA_1"),
674 MT7988_TYPE0_PIN(49, "EMMC_DATA_0"),
675 MT7988_TYPE0_PIN(50, "PCM_FS_I2S_LRCK"),
676 MT7988_TYPE0_PIN(51, "PCM_CLK_I2S_BCLK"),
677 MT7988_TYPE0_PIN(52, "PCM_DRX_I2S_DIN"),
678 MT7988_TYPE0_PIN(53, "PCM_DTX_I2S_DOUT"),
679 MT7988_TYPE0_PIN(54, "PCM_MCK_I2S_MCLK"),
680 MT7988_TYPE0_PIN(55, "UART0_RXD"),
681 MT7988_TYPE0_PIN(56, "UART0_TXD"),
682 MT7988_TYPE0_PIN(57, "PWMD0"),
683 MT7988_TYPE0_PIN(58, "JTAG_JTDI"),
684 MT7988_TYPE0_PIN(59, "JTAG_JTDO"),
685 MT7988_TYPE0_PIN(60, "JTAG_JTMS"),
686 MT7988_TYPE0_PIN(61, "JTAG_JTCLK"),
687 MT7988_TYPE0_PIN(62, "JTAG_JTRST_N"),
688 MT7988_TYPE1_PIN(63, "USB_DRV_VBUS_P1"),
689 MT7988_TYPE0_PIN(64, "LED_A"),
690 MT7988_TYPE0_PIN(65, "LED_B"),
691 MT7988_TYPE0_PIN(66, "LED_C"),
692 MT7988_TYPE0_PIN(67, "LED_D"),
693 MT7988_TYPE0_PIN(68, "LED_E"),
694 MT7988_TYPE0_PIN(69, "GPIO_B"),
695 MT7988_TYPE0_PIN(70, "GPIO_C"),
696 MT7988_TYPE2_PIN(71, "I2C_2_SCL"),
697 MT7988_TYPE2_PIN(72, "I2C_2_SDA"),
698 MT7988_TYPE0_PIN(73, "PCIE30_2L_1_PRESET_N"),
699 MT7988_TYPE0_PIN(74, "PCIE30_1L_0_PRESET_N"),
700 MT7988_TYPE1_PIN(75, "PCIE30_2L_1_WAKE_N"),
701 MT7988_TYPE1_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
702 MT7988_TYPE1_PIN(77, "PCIE30_1L_0_WAKE_N"),
703 MT7988_TYPE1_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
704 MT7988_TYPE1_PIN(79, "USB_DRV_VBUS_P0"),
705 MT7988_TYPE0_PIN(80, "UART1_RXD"),
706 MT7988_TYPE0_PIN(81, "UART1_TXD"),
707 MT7988_TYPE0_PIN(82, "UART1_CTS"),
708 MT7988_TYPE0_PIN(83, "UART1_RTS"),
709};
710
711/* jtag */
712static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
713static const int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
714
715static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
716static const int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
717
718static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
719static const int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
720
721static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
722static const int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
723
724static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
725static const int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
726
727static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
728static const int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
729
730/* int_usxgmii */
731static const int mt7988_int_usxgmii_pins[] = { 2, 3 };
732static const int mt7988_int_usxgmii_funcs[] = { 3, 3 };
733
734/* pwm */
735static const int mt7988_pwm0_pins[] = { 57 };
736static const int mt7988_pwm0_funcs[] = { 1 };
737
738static const int mt7988_pwm1_pins[] = { 21 };
739static const int mt7988_pwm1_funcs[] = { 1 };
740
741static const int mt7988_pwm2_pins[] = { 80 };
742static const int mt7988_pwm2_funcs[] = { 2 };
743
744static const int mt7988_pwm3_pins[] = { 81 };
745static const int mt7988_pwm3_funcs[] = { 2 };
746
747static const int mt7988_pwm4_pins[] = { 82 };
748static const int mt7988_pwm4_funcs[] = { 2 };
749
750static const int mt7988_pwm5_pins[] = { 83 };
751static const int mt7988_pwm5_funcs[] = { 2 };
752
753static const int mt7988_pwm6_pins[] = { 69 };
754static const int mt7988_pwm6_funcs[] = { 3 };
755
756static const int mt7988_pwm7_pins[] = { 70 };
757static const int mt7988_pwm7_funcs[] = { 3 };
758
759/* dfd */
760static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
761static const int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
762
763/* i2c */
764static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
765static const int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
766
767static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
768static const int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
769
770static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
771static const int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
772
773static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
774static const int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
775
776static const int mt7988_i2c0_0_pins[] = { 5, 6 };
777static const int mt7988_i2c0_0_funcs[] = { 2, 2 };
778
779static const int mt7988_i2c1_sfp_pins[] = { 5, 6 };
780static const int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
781
782static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
783static const int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
784
785static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
786static const int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
787
788static const int mt7988_i2c0_1_pins[] = { 15, 16 };
789static const int mt7988_i2c0_1_funcs[] = { 1, 1 };
790
791static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
792static const int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
793
794static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
795static const int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
796
797static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
798static const int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
799
800static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
801static const int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
802
803static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
804static const int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
805
806static const int mt7988_i2c1_0_pins[] = { 17, 18 };
807static const int mt7988_i2c1_0_funcs[] = { 1, 1 };
808
809static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
810static const int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
811
812static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
813static const int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
814
815static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
816static const int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
817
818static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
819static const int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
820
821static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
822static const int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
823
824static const int mt7988_i2c1_2_pins[] = { 69, 70 };
825static const int mt7988_i2c1_2_funcs[] = { 2, 2 };
826
827static const int mt7988_i2c2_0_pins[] = { 69, 70 };
828static const int mt7988_i2c2_0_funcs[] = { 4, 4 };
829
830static const int mt7988_i2c2_1_pins[] = { 71, 72 };
831static const int mt7988_i2c2_1_funcs[] = { 1, 1 };
832
833/* eth */
834static const int mt7988_mdc_mdio0_pins[] = { 5, 6 };
835static const int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
836
837static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
838static const int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
839
840static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
841static const int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
842
843static const int mt7988_mdc_mdio1_pins[] = { 69, 70 };
844static const int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
845
846/* pcie */
847static const int mt7988_pcie_wake_n0_0_pins[] = { 7 };
848static const int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
849
850static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
851static const int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
852
853static const int mt7988_pcie_wake_n3_0_pins[] = { 9 };
854static const int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
855
856static const int mt7988_pcie_clk_req_n3_pins[] = { 10 };
857static const int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
858
859static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
860static const int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
861
862static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
863static const int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
864
865static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
866static const int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
867
868static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
869static const int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
870
871static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
872static const int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
873
874static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
875static const int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
876
877static const int mt7988_pcie_wake_n0_1_pins[] = { 13 };
878static const int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
879
880static const int mt7988_pcie_wake_n3_1_pins[] = { 14 };
881static const int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
882
883static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
884static const int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
885
886static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
887static const int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
888
889static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
890static const int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
891
892static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
893static const int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
894
895static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
896static const int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
897
898static const int mt7988_pcie_wake_n1_0_pins[] = { 75 };
899static const int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
900
901static const int mt7988_pcie_clk_req_n1_pins[] = { 76 };
902static const int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
903
904static const int mt7988_pcie_wake_n2_0_pins[] = { 77 };
905static const int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
906
907static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
908static const int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
909
910static const int mt7988_pcie_wake_n2_1_pins[] = { 79 };
911static const int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
912
913/* pmic */
914static const int mt7988_pmic_pins[] = { 11 };
915static const int mt7988_pmic_funcs[] = { 1 };
916
917/* watchdog */
918static const int mt7988_watchdog_pins[] = { 12 };
919static const int mt7988_watchdog_funcs[] = { 1 };
920
921/* spi */
922static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
923static const int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
924
925static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
926static const int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
927
928static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
929static const int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
930
931static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
932static const int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
933
934static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
935static const int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
936
937/* flash */
938static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
939static const int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
940
941static const int mt7988_emmc_45_pins[] = {
942 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 };
943static const int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
944
945static const int mt7988_emmc_51_pins[] = {
946 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 };
947static const int mt7988_emmc_51_funcs[] = {
948 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
949
950/* uart */
951static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
952static const int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
953
954static const int mt7988_tops_uart0_0_pins[] = { 22, 23 };
955static const int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
956
957static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
958static const int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
959
960static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
961static const int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
962
963static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
964static const int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
965
966static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
967static const int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
968
969static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
970static const int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
971
972static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
973static const int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
974
975static const int mt7988_tops_uart1_0_pins[] = { 28, 29 };
976static const int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
977
978static const int mt7988_tops_uart0_1_pins[] = { 30, 31 };
979static const int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
980
981static const int mt7988_tops_uart1_1_pins[] = { 36, 37 };
982static const int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
983
984static const int mt7988_uart0_pins[] = { 55, 56 };
985static const int mt7988_uart0_funcs[] = { 1, 1 };
986
987static const int mt7988_tops_uart0_2_pins[] = { 55, 56 };
988static const int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
989
990static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
991static const int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
992
993static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
994static const int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
995
996static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
997static const int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
998
999static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
1000static const int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
1001
1002static const int mt7988_tops_uart1_2_pins[] = { 80, 81 };
1003static const int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
1004
1005static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
1006static const int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
1007
1008static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
1009static const int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
1010
1011static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
1012static const int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
1013
1014/* udi */
1015static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
1016static const int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
1017
1018/* pcm */
1019static const int mt7988_pcm_pins[] = { 50, 51, 52, 53, 54 };
1020static const int mt7988_pcm_funcs[] = { 1, 1, 1, 1, 1 };
1021
1022/* led */
1023static const int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 };
1024static const int mt7988_gbe_led1_funcs[] = { 6, 6, 6, 6 };
1025
1026static const int mt7988_2p5gbe_led1_pins[] = { 62 };
1027static const int mt7988_2p5gbe_led1_funcs[] = { 6 };
1028
1029static const int mt7988_gbe_led0_pins[] = { 64, 65, 66, 67 };
1030static const int mt7988_gbe_led0_funcs[] = { 1, 1, 1, 1 };
1031
1032static const int mt7988_2p5gbe_led0_pins[] = { 68 };
1033static const int mt7988_2p5gbe_led0_funcs[] = { 1 };
1034
1035/* usb */
1036static const int mt7988_drv_vbus_p1_pins[] = { 63 };
1037static const int mt7988_drv_vbus_p1_funcs[] = { 1 };
1038
1039static const int mt7988_drv_vbus_pins[] = { 79 };
1040static const int mt7988_drv_vbus_funcs[] = { 1 };
1041
1042static const struct mtk_group_desc mt7988_groups[] = {
1043 PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
1044 PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
1045 PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
1046 PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
1047 PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
1048 PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
1049 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
1050 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
1051 PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
1052 PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
1053 PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
1054 PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
1055 PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
1056 PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
1057 PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
1058 PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
1059 PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
1060 PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
1061 PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
1062 PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
1063 PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
1064 PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
1065 PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
1066 PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
1067 PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
1068 PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
1069 PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
1070 PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
1071 PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
1072 PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
1073 PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
1074 PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
1075 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
1076 PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
1077 PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
1078 PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
1079 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
1080 PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
1081 PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
1082 PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
1083 PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
1084 PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
1085 PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
1086 PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
1087 PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
1088 PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
1089 PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
1090 PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
1091 PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
1092 PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
1093 PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
1094 PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
1095 PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
1096 PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
1097 PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
1098 PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
1099 PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
1100 PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
1101 PINCTRL_PIN_GROUP("udi", mt7988_udi),
1102 PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
1103 PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
1104 PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
1105 PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
1106 PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
1107 PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
1108 PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
1109 PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
1110 PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
1111 PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
1112 PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
1113 PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
1114 PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
1115 PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
1116 PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
1117 PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
1118 PINCTRL_PIN_GROUP("gbe_led1", mt7988_gbe_led1),
1119 PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
1120 PINCTRL_PIN_GROUP("gbe_led0", mt7988_gbe_led0),
1121 PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
1122 PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
1123 PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
1124 PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
1125 PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
1126 PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
1127 PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
1128 PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
1129 PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
1130 PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
1131 PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
1132 PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
1133 PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
1134 PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
1135 PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
1136 PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
1137 PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
1138 PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
1139 PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
1140 PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
1141 PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
1142 PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
1143 PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
1144 PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
1145 PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
1146 PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
1147 PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
1148 PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
1149 PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
1150};
1151
1152static const struct mtk_io_type_desc mt7988_io_type_desc[] = {
1153 [IO_TYPE_GRP0] = {
1154 .name = "18OD33",
1155 .bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
1156 .drive_set = mtk_pinconf_drive_set_v1,
1157 .input_enable = mtk_pinconf_input_enable_v1,
1158 },
1159 [IO_TYPE_GRP1] = {
1160 .name = "18A01",
1161 .bias_set = mtk_pinconf_bias_set_pu_pd,
1162 .drive_set = mtk_pinconf_drive_set_v1,
1163 .input_enable = mtk_pinconf_input_enable_v1,
1164 },
1165 [IO_TYPE_GRP2] = {
1166 .name = "I2C",
1167 .input_enable = mtk_pinconf_input_enable_v1,
1168 },
1169};
1170
1171/* Joint those groups owning the same capability in user point of view which
1172 * allows that people tend to use through the device tree.
1173 */
1174static const char *const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag",
1175 "wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", };
1176static const char *const mt7988_int_usxgmii_groups[] = { "int_usxgmii", };
1177static const char *const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3",
1178 "pwm4", "pwm5", "pwm6", "pwm7" };
1179static const char *const mt7988_dfd_groups[] = { "dfd", };
1180static const char *const mt7988_i2c_groups[] = { "xfi_phy0_i2c0",
1181 "xfi_phy1_i2c0", "xfi_phy_pll_i2c0", "xfi_phy_pll_i2c1", "i2c0_0",
1182 "i2c1_sfp", "xfi_pextp_phy0_i2c", "xfi_pextp_phy1_i2c", "i2c0_1",
1183 "u30_phy_i2c0", "u32_phy_i2c0", "xfi_phy0_i2c1", "xfi_phy1_i2c1",
1184 "xfi_phy_pll_i2c2", "i2c1_0", "u30_phy_i2c1", "u32_phy_i2c1",
1185 "xfi_phy_pll_i2c3", "sgmii0_i2c", "sgmii1_i2c", "i2c1_2", "i2c2_0",
1186 "i2c2_1", };
1187static const char *const mt7988_ethernet_groups[] = { "mdc_mdio0",
1188 "2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", };
1189static const char *const mt7988_pcie_groups[] = { "pcie_wake_n0_0",
1190 "pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3",
1191 "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2",
1192 "pcie_p2_phy_i2c", "ckm_phy_i2c", "pcie_wake_n0_1", "pcie_wake_n3_1",
1193 "pcie_2l_0_pereset", "pcie_1l_1_pereset", "pcie_clk_req_n2_1",
1194 "pcie_2l_1_perese", "pcie_1l_0_pereset", "pcie_wake_n1_0",
1195 "cie_clk_req_n1", "pcie_wake_n2_0", "pcie_wake_n2_1", };
1196static const char *const mt7988_pmic_groups[] = { "pmic", };
1197static const char *const mt7988_wdt_groups[] = { "watchdog", };
1198static const char *const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold",
1199 "spi1", "spi2", "spi2_wp_hold", };
1200static const char *const mt7988_flash_groups[] = { "emmc_45", "snfi",
1201 "emmc_51" };
1202static const char *const mt7988_uart_groups[] = { "uart2", "tops_uart0_0",
1203 "uart2_0", "uart1_0", "uart2_1",
1204 "net_wo0_uart_txd_0", "net_wo1_uart_txd_0", "net_wo2_uart_txd_0",
1205 "tops_uart1_0", "ops_uart0_1", "ops_uart1_1",
1206 "uart0", "tops_uart0_2", "uart1_1",
1207 "uart2_3", "uart1_2", "tops_uart1_2",
1208 "net_wo0_uart_txd_1", "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", };
1209static const char *const mt7988_udi_groups[] = { "udi", };
1210static const char *const mt7988_pcm_groups[] = { "pcm", };
1211static const char *const mt7988_led_groups[] = { "gbe_led1", "2p5gbe_led1",
1212 "gbe_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", };
1213static const char *const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", };
1214
1215static const struct mtk_function_desc mt7988_functions[] = {
1216 {"jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups)},
1217 {"int_usxgmii", mt7988_int_usxgmii_groups,
1218 ARRAY_SIZE(mt7988_int_usxgmii_groups)},
1219 {"pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups)},
1220 {"dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups)},
1221 {"i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups)},
1222 {"eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups)},
1223 {"pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups)},
1224 {"pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups)},
1225 {"watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups)},
1226 {"spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups)},
1227 {"flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups)},
1228 {"uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups)},
1229 {"udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups)},
1230 {"pcm", mt7988_pcm_groups, ARRAY_SIZE(mt7988_pcm_groups)},
1231 {"usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups)},
1232 {"led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups)},
1233};
1234
1235static const char *const mt7988_pinctrl_register_base_names[] = {
1236 "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base",
1237 "iocfg_lb_base", "iocfg_tl_base",
1238};
1239
1240static const struct mtk_pinctrl_soc mt7988_data = {
1241 .name = "mt7988_pinctrl",
1242 .reg_cal = mt7988_reg_cals,
1243 .pins = mt7988_pins,
1244 .npins = ARRAY_SIZE(mt7988_pins),
1245 .grps = mt7988_groups,
1246 .ngrps = ARRAY_SIZE(mt7988_groups),
1247 .funcs = mt7988_functions,
1248 .nfuncs = ARRAY_SIZE(mt7988_functions),
1249 .io_type = mt7988_io_type_desc,
1250 .ntype = ARRAY_SIZE(mt7988_io_type_desc),
1251 .gpio_mode = 0,
1252 .base_names = mt7988_pinctrl_register_base_names,
1253 .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
1254 .base_calc = 1,
1255};
1256
1257static int mtk_pinctrl_mt7988_probe(struct udevice *dev)
1258{
1259 return mtk_pinctrl_common_probe(dev, &mt7988_data);
1260}
1261
1262static const struct udevice_id mt7988_pctrl_match[] = {
1263 {.compatible = "mediatek,mt7988-pinctrl"},
1264 { /* sentinel */ }
1265};
1266
1267U_BOOT_DRIVER(mt7988_pinctrl) = {
1268 .name = "mt7988_pinctrl",
1269 .id = UCLASS_PINCTRL,
1270 .of_match = mt7988_pctrl_match,
1271 .ops = &mtk_pinctrl_ops,
1272 .probe = mtk_pinctrl_mt7988_probe,
1273 .priv_auto = sizeof(struct mtk_pinctrl_priv),
1274};