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git01.mediatek.com / filogic / uboot / 7bdd82c90ef99c184afdd8d7fce25eef75a8f6dc / . / arch / arm / dts / fsl-imx8qm-mek.dts
blob: 6cf7ce3d5e03ed6c8be0aac8a4a4a5ded3338ee1 [file] [log] [blame]
Peng Fan203a2272019-03-05 02:32:49 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017-2018 NXP
4 */
5
6/dts-v1/;
7
8#include "fsl-imx8qm.dtsi"
Peng Fan203a2272019-03-05 02:32:49 +0000[diff] [blame]9
10/ {
11 model = "Freescale i.MX8QM MEK";
12 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
13
14 chosen {
15 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
16 stdout-path = &lpuart0;
17 };
18
19 reg_usdhc2_vmmc: usdhc2_vmmc {
20 compatible = "regulator-fixed";
21 regulator-name = "sw-3p3-sd1";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
25 off-on-delay = <4800>;
26 enable-active-high;
27 };
28};
29
30&iomuxc {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_hog>;
33
34 imx8qm-mek {
35 pinctrl_hog: hoggrp {
36 fsl,pins = <
37 SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c
38 SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c
39 SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c
40 >;
41 };
42
43 pinctrl_fec1: fec1grp {
44 fsl,pins = <
45 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
46 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
47 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
48 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
49 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061
50 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
51 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
52 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061
53 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061
54 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061
55 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
56 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
57 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
58 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061
59 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061
60 >;
61 };
62
63 pinctrl_fec2: fec2grp {
64 fsl,pins = <
65 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
66 SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
67 SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
68 SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
69 SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
70 SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
71 SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
72 SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
73 SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
74 SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
75 SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
76 SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
77 SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
78 >;
79 };
80
81 pinctrl_lpuart0: lpuart0grp {
82 fsl,pins = <
83 SC_P_UART0_RX_DMA_UART0_RX 0x06000020
84 SC_P_UART0_TX_DMA_UART0_TX 0x06000020
85 >;
86 };
87
88 pinctrl_usdhc1: usdhc1grp {
89 fsl,pins = <
90 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
91 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
92 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
93 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
94 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
95 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
96 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
97 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
98 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
99 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
100 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
101 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
102 >;
103 };
104
105 pinctrl_usdhc2_gpio: usdhc2grpgpio {
106 fsl,pins = <
107 SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
108 SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
109 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
110 >;
111 };
112
113 pinctrl_usdhc2: usdhc2grp {
114 fsl,pins = <
115 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
116 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
117 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
118 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
119 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
120 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
121 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
122 >;
123 };
124 };
125};
126
127&usdhc1 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_usdhc1>;
130 bus-width = <8>;
131 non-removable;
132 status = "okay";
133};
134
135&usdhc2 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
138 bus-width = <4>;
139 cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
140 wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
141 vmmc-supply = <&reg_usdhc2_vmmc>;
142 status = "okay";
143};
144
145&fec1 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_fec1>;
148 phy-mode = "rgmii-txid";
149 phy-handle = <&ethphy0>;
150 fsl,magic-packet;
151 fsl,rgmii_rxc_dly;
152 status = "okay";
153
154 mdio {
155 #address-cells = <1>;
156 #size-cells = <0>;
157
158 ethphy0: ethernet-phy@0 {
159 compatible = "ethernet-phy-ieee802.3-c22";
160 reg = <0>;
161 at803x,eee-disabled;
162 at803x,vddio-1p8v;
163 };
164
165 ethphy1: ethernet-phy@1 {
166 compatible = "ethernet-phy-ieee802.3-c22";
167 reg = <1>;
168 at803x,eee-disabled;
169 at803x,vddio-1p8v;
170 status = "disabled";
171 };
172 };
173};
174
175&lpuart0 { /* console */
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_lpuart0>;
178 status = "okay";
179};
180
181&gpio1 {
182 status = "okay";
183};