blob: 971acbb6dffaf4716b70d742a526f760cd858ab3 [file] [log] [blame]
Michal Simek0dd222b2013-04-22 14:56:49 +02001/*
2 * (C) Copyright 2013 Inc.
3 *
4 * Xilinx Zynq SD Host Controller Interface
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Michal Simek0dd222b2013-04-22 14:56:49 +02007 */
8
9#include <common.h>
Michal Simekc57ba042014-02-24 11:16:31 +010010#include <fdtdec.h>
11#include <libfdt.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020012#include <malloc.h>
13#include <sdhci.h>
14#include <asm/arch/sys_proto.h>
15
Michal Simek384081a2015-01-14 16:11:47 +010016int zynq_sdhci_init(phys_addr_t regbase)
Michal Simek0dd222b2013-04-22 14:56:49 +020017{
18 struct sdhci_host *host = NULL;
19
20 host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
21 if (!host) {
22 printf("zynq_sdhci_init: sdhci_host malloc fail\n");
23 return 1;
24 }
25
26 host->name = "zynq_sdhci";
27 host->ioaddr = (void *)regbase;
Siva Durga Prasad Paladugu049e0032014-07-08 15:31:04 +053028 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
Siva Durga Prasad Paladugu0d6891b2014-01-22 09:17:09 +010029 SDHCI_QUIRK_BROKEN_R1B;
Michal Simek0dd222b2013-04-22 14:56:49 +020030 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
31
Michal Simek0dd222b2013-04-22 14:56:49 +020032 add_sdhci(host, 52000000, 52000000 >> 9);
33 return 0;
34}
Michal Simekc57ba042014-02-24 11:16:31 +010035
36#ifdef CONFIG_OF_CONTROL
37int zynq_sdhci_of_init(const void *blob)
38{
39 int offset = 0;
40 u32 ret = 0;
Michal Simek384081a2015-01-14 16:11:47 +010041 phys_addr_t reg;
Michal Simekc57ba042014-02-24 11:16:31 +010042
43 debug("ZYNQ SDHCI: Initialization\n");
44
45 do {
46 offset = fdt_node_offset_by_compatible(blob, offset,
47 "arasan,sdhci-8.9a");
48 if (offset != -1) {
49 reg = fdtdec_get_addr(blob, offset, "reg");
50 if (reg != FDT_ADDR_T_NONE) {
51 ret |= zynq_sdhci_init(reg);
52 } else {
53 debug("ZYNQ SDHCI: Can't get base address\n");
54 return -1;
55 }
56 }
57 } while (offset != -1);
58
59 return ret;
60}
61#endif