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Minkyu Kangb1b24682011-01-24 15:22:23 +09001/*
2 * (C) Copyright 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 *
20 */
21
Chander Kashyap4131a772011-12-06 23:34:12 +000022#ifndef _EXYNOS4_CPU_H
23#define _EXYNOS4_CPU_H
Minkyu Kangb1b24682011-01-24 15:22:23 +090024
Chander Kashyap34076a02012-02-05 23:01:46 +000025#define DEVICE_NOT_AVAILABLE 0
26
Minkyu Kangf92e88e2012-04-26 15:48:32 +090027#define EXYNOS_CPU_NAME "Exynos"
Chander Kashyap4131a772011-12-06 23:34:12 +000028#define EXYNOS4_ADDR_BASE 0x10000000
Minkyu Kangb1b24682011-01-24 15:22:23 +090029
Chander Kashyap4131a772011-12-06 23:34:12 +000030/* EXYNOS4 */
31#define EXYNOS4_GPIO_PART3_BASE 0x03860000
32#define EXYNOS4_PRO_ID 0x10000000
Donghwa Lee09552712012-04-05 19:36:10 +000033#define EXYNOS4_SYSREG_BASE 0x10010000
Chander Kashyap4131a772011-12-06 23:34:12 +000034#define EXYNOS4_POWER_BASE 0x10020000
35#define EXYNOS4_SWRESET 0x10020400
36#define EXYNOS4_CLOCK_BASE 0x10030000
37#define EXYNOS4_SYSTIMER_BASE 0x10050000
38#define EXYNOS4_WATCHDOG_BASE 0x10060000
39#define EXYNOS4_MIU_BASE 0x10600000
40#define EXYNOS4_DMC0_BASE 0x10400000
41#define EXYNOS4_DMC1_BASE 0x10410000
42#define EXYNOS4_GPIO_PART2_BASE 0x11000000
43#define EXYNOS4_GPIO_PART1_BASE 0x11400000
44#define EXYNOS4_FIMD_BASE 0x11C00000
Donghwa Lee09552712012-04-05 19:36:10 +000045#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
Chander Kashyap4131a772011-12-06 23:34:12 +000046#define EXYNOS4_USBOTG_BASE 0x12480000
47#define EXYNOS4_MMC_BASE 0x12510000
48#define EXYNOS4_SROMC_BASE 0x12570000
Rajeshwari Shindedad39d42012-05-21 16:38:03 +053049#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000
Chander Kashyap4131a772011-12-06 23:34:12 +000050#define EXYNOS4_USBPHY_BASE 0x125B0000
51#define EXYNOS4_UART_BASE 0x13800000
Rajeshwari Shindebb5e46e2012-07-23 21:23:49 +000052#define EXYNOS4_I2C_BASE 0x13860000
Chander Kashyap4131a772011-12-06 23:34:12 +000053#define EXYNOS4_ADC_BASE 0x13910000
54#define EXYNOS4_PWMTIMER_BASE 0x139D0000
55#define EXYNOS4_MODEM_BASE 0x13A00000
Chander Kashyap34076a02012-02-05 23:01:46 +000056#define EXYNOS4_USBPHY_CONTROL 0x10020704
57
58#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
59
60/* EXYNOS5 */
Rajeshwari Shinde2535e912012-07-23 21:23:50 +000061#define EXYNOS5_I2C_SPACING 0x10000
62
Chander Kashyap34076a02012-02-05 23:01:46 +000063#define EXYNOS5_GPIO_PART4_BASE 0x03860000
64#define EXYNOS5_PRO_ID 0x10000000
65#define EXYNOS5_CLOCK_BASE 0x10010000
66#define EXYNOS5_POWER_BASE 0x10040000
67#define EXYNOS5_SWRESET 0x10040400
68#define EXYNOS5_SYSREG_BASE 0x10050000
69#define EXYNOS5_WATCHDOG_BASE 0x101D0000
70#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
71#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
72#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
73#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
74#define EXYNOS5_GPIO_PART1_BASE 0x11400000
Donghwa Lee09552712012-04-05 19:36:10 +000075#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
Rajeshwari Shindedad39d42012-05-21 16:38:03 +053076#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
Rajeshwari Shinde0f91f132012-05-14 05:52:04 +000077#define EXYNOS5_USBPHY_BASE 0x12130000
78#define EXYNOS5_USBOTG_BASE 0x12140000
Chander Kashyap34076a02012-02-05 23:01:46 +000079#define EXYNOS5_MMC_BASE 0x12200000
80#define EXYNOS5_SROMC_BASE 0x12250000
Chander Kashyap34076a02012-02-05 23:01:46 +000081#define EXYNOS5_UART_BASE 0x12C00000
Rajeshwari Shindebb5e46e2012-07-23 21:23:49 +000082#define EXYNOS5_I2C_BASE 0x12C60000
Chander Kashyap34076a02012-02-05 23:01:46 +000083#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
84#define EXYNOS5_GPIO_PART2_BASE 0x13400000
85#define EXYNOS5_FIMD_BASE 0x14400000
86
87#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
88#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
Minkyu Kangb1b24682011-01-24 15:22:23 +090089
90#ifndef __ASSEMBLY__
91#include <asm/io.h>
92/* CPU detection macros */
93extern unsigned int s5p_cpu_id;
Minkyu Kang13398722011-05-16 19:45:54 +090094extern unsigned int s5p_cpu_rev;
95
96static inline int s5p_get_cpu_rev(void)
97{
98 return s5p_cpu_rev;
99}
Minkyu Kangb1b24682011-01-24 15:22:23 +0900100
101static inline void s5p_set_cpu_id(void)
102{
Minkyu Kangf92e88e2012-04-26 15:48:32 +0900103 unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
Minkyu Kangb1b24682011-01-24 15:22:23 +0900104
Minkyu Kangf92e88e2012-04-26 15:48:32 +0900105 switch (pro_id) {
106 case 0x200:
107 /* Exynos4210 EVT0 */
108 s5p_cpu_id = 0x4210;
Minkyu Kang13398722011-05-16 19:45:54 +0900109 s5p_cpu_rev = 0;
Minkyu Kangf92e88e2012-04-26 15:48:32 +0900110 break;
111 case 0x210:
112 /* Exynos4210 EVT1 */
113 s5p_cpu_id = 0x4210;
114 break;
115 case 0x412:
116 /* Exynos4412 */
117 s5p_cpu_id = 0x4412;
118 break;
119 case 0x520:
120 /* Exynos5250 */
121 s5p_cpu_id = 0x5250;
122 break;
Minkyu Kang13398722011-05-16 19:45:54 +0900123 }
Minkyu Kangb1b24682011-01-24 15:22:23 +0900124}
125
Minkyu Kangf92e88e2012-04-26 15:48:32 +0900126static inline char *s5p_get_cpu_name(void)
127{
128 return EXYNOS_CPU_NAME;
129}
130
Minkyu Kangb1b24682011-01-24 15:22:23 +0900131#define IS_SAMSUNG_TYPE(type, id) \
132static inline int cpu_is_##type(void) \
133{ \
Minkyu Kangf92e88e2012-04-26 15:48:32 +0900134 return (s5p_cpu_id >> 12) == id; \
Minkyu Kangb1b24682011-01-24 15:22:23 +0900135}
136
Minkyu Kangf92e88e2012-04-26 15:48:32 +0900137IS_SAMSUNG_TYPE(exynos4, 0x4)
138IS_SAMSUNG_TYPE(exynos5, 0x5)
Minkyu Kangb1b24682011-01-24 15:22:23 +0900139
140#define SAMSUNG_BASE(device, base) \
141static inline unsigned int samsung_get_base_##device(void) \
142{ \
Chander Kashyap4131a772011-12-06 23:34:12 +0000143 if (cpu_is_exynos4()) \
144 return EXYNOS4_##base; \
Chander Kashyap34076a02012-02-05 23:01:46 +0000145 else if (cpu_is_exynos5()) \
146 return EXYNOS5_##base; \
Minkyu Kangb1b24682011-01-24 15:22:23 +0900147 else \
148 return 0; \
149}
150
151SAMSUNG_BASE(adc, ADC_BASE)
152SAMSUNG_BASE(clock, CLOCK_BASE)
Donghwa Lee09552712012-04-05 19:36:10 +0000153SAMSUNG_BASE(sysreg, SYSREG_BASE)
Minkyu Kangb1b24682011-01-24 15:22:23 +0900154SAMSUNG_BASE(fimd, FIMD_BASE)
Rajeshwari Shindebb5e46e2012-07-23 21:23:49 +0000155SAMSUNG_BASE(i2c, I2C_BASE)
Donghwa Lee09552712012-04-05 19:36:10 +0000156SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
Minkyu Kangb1b24682011-01-24 15:22:23 +0900157SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
158SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
159SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
Chander Kashyap34076a02012-02-05 23:01:46 +0000160SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
Minkyu Kangb1b24682011-01-24 15:22:23 +0900161SAMSUNG_BASE(pro_id, PRO_ID)
162SAMSUNG_BASE(mmc, MMC_BASE)
163SAMSUNG_BASE(modem, MODEM_BASE)
164SAMSUNG_BASE(sromc, SROMC_BASE)
165SAMSUNG_BASE(swreset, SWRESET)
166SAMSUNG_BASE(timer, PWMTIMER_BASE)
167SAMSUNG_BASE(uart, UART_BASE)
168SAMSUNG_BASE(usb_phy, USBPHY_BASE)
Rajeshwari Shindedad39d42012-05-21 16:38:03 +0530169SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
Minkyu Kangb1b24682011-01-24 15:22:23 +0900170SAMSUNG_BASE(usb_otg, USBOTG_BASE)
171SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
HeungJun, Kimb3717272012-01-16 21:13:04 +0000172SAMSUNG_BASE(power, POWER_BASE)
Minkyu Kangb1b24682011-01-24 15:22:23 +0900173#endif
174
Chander Kashyap4131a772011-12-06 23:34:12 +0000175#endif /* _EXYNOS4_CPU_H */