blob: f3d3d18c055178db7b7886d433504f3ac8eaed84 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +02002/*
3 * am335x_sl50.h
4 *
5 * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +02006 */
7
8#ifndef __CONFIG_AM335X_EVM_H
9#define __CONFIG_AM335X_EVM_H
10
11#include <configs/ti_am335x_common.h>
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020012
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020013/* Clock Defines */
14#define V_OSCK 24000000 /* Clock output from T2 */
15#define V_SCLK (V_OSCK)
16
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020017#define MEM_LAYOUT_ENV_SETTINGS \
18 "scriptaddr=0x80000000\0" \
19 "pxefile_addr_r=0x80100000\0" \
20 "kernel_addr_r=0x82000000\0" \
21 "fdt_addr_r=0x88000000\0" \
22 "ramdisk_addr_r=0x88080000\0" \
23
24#define BOOT_TARGET_DEVICES(func) \
25 func(MMC, mmc, 0) \
26 func(MMC, mmc, 1)
27
28#define AM335XX_BOARD_FDTFILE \
29 "fdtfile=am335x-sl50.dtb\0" \
30
31#include <config_distro_bootcmd.h>
32
Tom Rinic9edebe2022-12-04 10:03:50 -050033#define CFG_EXTRA_ENV_SETTINGS \
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020034 AM335XX_BOARD_FDTFILE \
35 MEM_LAYOUT_ENV_SETTINGS \
36 BOOTENV
37
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020038/* NS16550 Configuration */
Tom Rinidf6a2152022-11-16 13:10:28 -050039#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
40#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
41#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
42#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
43#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
44#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020045
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020046#endif /* ! __CONFIG_AM335X_SL50_H */