blob: 29888b4e1c272d917a2ca704dd34dc6b1dfe1b38 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/***********************************************************
16 * High Level Configuration Options
17 * (easy to change)
18 ***********************************************************/
19#define CONFIG_405GP 1 /* This is a PPC405 CPU */
20#define CONFIG_4xx 1 /* ...member of PPC4xx family */
21#define CONFIG_PIP405 1 /* ...on a PIP405 board */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020022
23#define CONFIG_SYS_TEXT_BASE 0xFFF80000
24
wdenkc6097192002-11-03 00:24:07 +000025/***********************************************************
26 * Clock
27 ***********************************************************/
28#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
29
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050030
31/*
Jon Loeligerbeb9ff42007-07-10 09:22:23 -050032 * BOOTP options
33 */
34#define CONFIG_BOOTP_BOOTFILESIZE
35#define CONFIG_BOOTP_BOOTPATH
36#define CONFIG_BOOTP_GATEWAY
37#define CONFIG_BOOTP_HOSTNAME
38
39
40/*
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050041 * Command line configuration.
42 */
43#include <config_cmd_default.h>
44
45#define CONFIG_CMD_IDE
46#define CONFIG_CMD_DHCP
47#define CONFIG_CMD_PCI
48#define CONFIG_CMD_CACHE
49#define CONFIG_CMD_IRQ
50#define CONFIG_CMD_EEPROM
51#define CONFIG_CMD_I2C
52#define CONFIG_CMD_REGINFO
53#define CONFIG_CMD_FDC
54#define CONFIG_CMD_SCSI
55#define CONFIG_CMD_FAT
56#define CONFIG_CMD_DATE
57#define CONFIG_CMD_ELF
58#define CONFIG_CMD_USB
59#define CONFIG_CMD_MII
60#define CONFIG_CMD_SDRAM
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050061#define CONFIG_CMD_PING
62#define CONFIG_CMD_SAVES
63#define CONFIG_CMD_BSP
64
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#define CONFIG_SYS_HUSH_PARSER
wdenkc6097192002-11-03 00:24:07 +000066/**************************************************************
67 * I2C Stuff:
68 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
69 * 0x53.
70 * Caution: on the same bus is the SPD (Serial Presens Detect
71 * EEPROM of the SDRAM
72 * The Atmel EEPROM uses 16Bit addressing.
73 ***************************************************************/
Dirk Eibach42b204f2013-04-25 02:40:01 +000074#define CONFIG_SYS_I2C
75#define CONFIG_SYS_I2C_PPC4XX
76#define CONFIG_SYS_I2C_PPC4XX_CH0
77#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
78#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenkc6097192002-11-03 00:24:07 +000079
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
81#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +020082#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020083#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
84#define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
wdenkc6097192002-11-03 00:24:07 +000085
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
87#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
wdenkc6097192002-11-03 00:24:07 +000088 /* 64 byte page write mode using*/
89 /* last 6 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +000091
92
93/***************************************************************
94 * Definitions for Serial Presence Detect EEPROM address
95 * (to get SDRAM settings)
96 ***************************************************************/
97#define SPD_EEPROM_ADDRESS 0x50
98
wdenkda55c6e2004-01-20 23:12:12 +000099#define CONFIG_BOARD_EARLY_INIT_F
David Müller2e165b52011-12-22 13:38:20 +0100100#define CONFIG_BOARD_EARLY_INIT_R
101
wdenkc6097192002-11-03 00:24:07 +0000102/**************************************************************
103 * Environment definitions
104 **************************************************************/
105#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
106
107
108#define CONFIG_BOOTDELAY 5
109/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk7b4e3472005-08-13 02:04:37 +0200110/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200111#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
wdenkc6097192002-11-03 00:24:07 +0000112
113
wdenkb02744a2003-04-05 00:53:31 +0000114#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenkc6097192002-11-03 00:24:07 +0000115#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
116
117#define CONFIG_IPADDR 10.0.0.100
118#define CONFIG_SERVERIP 10.0.0.1
119#define CONFIG_PREBOOT
120/***************************************************************
121 * defines if the console is stored in the environment
122 ***************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
wdenkc6097192002-11-03 00:24:07 +0000124/***************************************************************
125 * defines if an overwrite_console function exists
126 *************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
128#define CONFIG_SYS_CONSOLE_INFO_QUIET
wdenkc6097192002-11-03 00:24:07 +0000129/***************************************************************
130 * defines if the overwrite_console should be stored in the
131 * environment
132 **************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
wdenkc6097192002-11-03 00:24:07 +0000134
135/**************************************************************
136 * loads config
137 *************************************************************/
138#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +0000140
wdenk2c9b05d2003-09-10 22:30:53 +0000141#define CONFIG_MISC_INIT_R
wdenkc6097192002-11-03 00:24:07 +0000142/***********************************************************
143 * Miscellaneous configurable options
144 **********************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500146#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000148#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000150#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
152#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
153#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000154
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
156#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000157
Stefan Roese3ddce572010-09-20 16:05:31 +0200158#define CONFIG_CONS_INDEX 1 /* Use UART0 */
159#define CONFIG_SYS_NS16550
160#define CONFIG_SYS_NS16550_SERIAL
161#define CONFIG_SYS_NS16550_REG_SIZE 1
162#define CONFIG_SYS_NS16550_CLK get_serial_clock()
163
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
165#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000166
167/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkc6097192002-11-03 00:24:07 +0000169 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
170 57600, 115200, 230400, 460800, 921600 }
171
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
173#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000174
wdenkc6097192002-11-03 00:24:07 +0000175/*-----------------------------------------------------------------------
176 * PCI stuff
177 *-----------------------------------------------------------------------
178 */
179#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
180#define PCI_HOST_FORCE 1 /* configure as pci host */
181#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
182
183#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000184#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkc6097192002-11-03 00:24:07 +0000185#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
186#define CONFIG_PCI_PNP /* pci plug-and-play */
187 /* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
189#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
190#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
191#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
192#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
193#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
194#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
195#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000196
197/*-----------------------------------------------------------------------
198 * Start addresses for the final memory configuration
199 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000201 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_SDRAM_BASE 0x00000000
203#define CONFIG_SYS_FLASH_BASE 0xFFF80000
204#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
205#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
206#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000207
208/*
209 * For booting Linux, the board info and command line data
210 * have to be in the first 8 MB of memory, since this is
211 * the maximum mapped by the Linux kernel during initialization.
212 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200213#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000214/*-----------------------------------------------------------------------
215 * FLASH organization
216 */
David Müller2e165b52011-12-22 13:38:20 +0100217#define CONFIG_SYS_UPDATE_FLASH_SIZE
218#define CONFIG_SYS_FLASH_PROTECTION
219#define CONFIG_SYS_FLASH_EMPTY_INFO
220
221#define CONFIG_SYS_FLASH_CFI
222#define CONFIG_FLASH_CFI_DRIVER
223
224#define CONFIG_FLASH_SHOW_PROGRESS 45
wdenkc6097192002-11-03 00:24:07 +0000225
David Müller2e165b52011-12-22 13:38:20 +0100226#define CONFIG_SYS_MAX_FLASH_BANKS 1
227#define CONFIG_SYS_MAX_FLASH_SECT 256
wdenkc6097192002-11-03 00:24:07 +0000228
wdenkc6097192002-11-03 00:24:07 +0000229/*
230 * Init Memory Controller:
231 */
wdenk2c9b05d2003-09-10 22:30:53 +0000232#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
233#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
234/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
235#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenkc6097192002-11-03 00:24:07 +0000236
wdenkda55c6e2004-01-20 23:12:12 +0000237#define CONFIG_BOARD_EARLY_INIT_F
wdenkc6097192002-11-03 00:24:07 +0000238
239/* Configuration Port location */
240#define CONFIG_PORT_ADDR 0xF4000000
241#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
242
243
wdenkc6097192002-11-03 00:24:07 +0000244/*-----------------------------------------------------------------------
245 * Definitions for initial stack pointer and data area (in On Chip SRAM)
246 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200247#define CONFIG_SYS_TEMP_STACK_OCM 1
248#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
249#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
250#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200251#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200252#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200253#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000254
wdenkc6097192002-11-03 00:24:07 +0000255/***********************************************************************
256 * External peripheral base address
257 ***********************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200258#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
wdenkc6097192002-11-03 00:24:07 +0000259
260/***********************************************************************
261 * Last Stage Init
262 ***********************************************************************/
263#define CONFIG_LAST_STAGE_INIT
264/************************************************************
265 * Ethernet Stuff
266 ***********************************************************/
Ben Warren3a918a62008-10-27 23:50:15 -0700267#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +0000268#define CONFIG_MII 1 /* MII PHY management */
269#define CONFIG_PHY_ADDR 1 /* PHY address */
wdenkc6097192002-11-03 00:24:07 +0000270/************************************************************
271 * RTC
272 ***********************************************************/
273#define CONFIG_RTC_MC146818
274#undef CONFIG_WATCHDOG /* watchdog disabled */
275
276/************************************************************
277 * IDE/ATA stuff
278 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
280#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000281
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
283#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
284#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
285#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
286#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
287#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenkc6097192002-11-03 00:24:07 +0000288
289#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
290#undef CONFIG_IDE_LED /* no led for ide supported */
291#define CONFIG_IDE_RESET /* reset for ide supported... */
292#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk2c9b05d2003-09-10 22:30:53 +0000293#define CONFIG_SUPPORT_VFAT
wdenkc6097192002-11-03 00:24:07 +0000294
295/************************************************************
296 * ATAPI support (experimental)
297 ************************************************************/
298#define CONFIG_ATAPI /* enable ATAPI Support */
299
300/************************************************************
301 * SCSI support (experimental) only SYM53C8xx supported
302 ************************************************************/
303#define CONFIG_SCSI_SYM53C8XX
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200304#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
305#define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
306#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
307#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
wdenkc6097192002-11-03 00:24:07 +0000308
309/************************************************************
310 * Disk-On-Chip configuration
311 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
313#define CONFIG_SYS_DOC_SHORT_TIMEOUT
314#define CONFIG_SYS_DOC_SUPPORT_2000
315#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
wdenkc6097192002-11-03 00:24:07 +0000316
317/************************************************************
318 * DISK Partition support
319 ************************************************************/
320#define CONFIG_DOS_PARTITION
321#define CONFIG_MAC_PARTITION
322#define CONFIG_ISO_PARTITION /* Experimental */
323
324/************************************************************
325 * Keyboard support
326 ************************************************************/
327#define CONFIG_ISA_KEYBOARD
328
329/************************************************************
330 * Video support
331 ************************************************************/
332#define CONFIG_VIDEO /*To enable video controller support */
333#define CONFIG_VIDEO_CT69000
334#define CONFIG_CFB_CONSOLE
335#define CONFIG_VIDEO_LOGO
336#define CONFIG_CONSOLE_EXTRA_INFO
337#define CONFIG_VGA_AS_SINGLE_DEVICE
338#define CONFIG_VIDEO_SW_CURSOR
339#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
340
341/************************************************************
342 * USB support
343 ************************************************************/
344#define CONFIG_USB_UHCI
345#define CONFIG_USB_KEYBOARD
346#define CONFIG_USB_STORAGE
347
348/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD2a7a0312009-05-16 12:14:54 +0200349#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
wdenkc6097192002-11-03 00:24:07 +0000350
351/************************************************************
352 * Debug support
353 ************************************************************/
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500354#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000355#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenkc6097192002-11-03 00:24:07 +0000356#endif
357
358/************************************************************
wdenk4ea537d2003-12-07 18:32:37 +0000359 * support BZIP2 compression
360 ************************************************************/
361#define CONFIG_BZIP2 1
362
363/************************************************************
wdenkc6097192002-11-03 00:24:07 +0000364 * Ident
365 ************************************************************/
366#define VERSION_TAG "released"
wdenke39c2842003-06-04 15:05:30 +0000367#define CONFIG_ISO_STRING "MEV-10066-001"
368#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
wdenkc6097192002-11-03 00:24:07 +0000369
370
371#endif /* __CONFIG_H */