| York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014, Freescale Semiconductor |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_ |
| 8 | #define _ASM_ARMV8_FSL_LSCH3_CONFIG_ |
| 9 | |
| 10 | #include <fsl_ddrc_version.h> |
| 11 | |
| 12 | #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ |
| 13 | /* Link Definitions */ |
| 14 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) |
| 15 | |
| 16 | #define CONFIG_SYS_IMMR 0x01000000 |
| 17 | #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) |
| 18 | #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) |
| 19 | #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) |
| 20 | #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) |
| 21 | #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) |
| 22 | #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) |
| 23 | #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) |
| 24 | #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) |
| 25 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) |
| 26 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) |
| 27 | #define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 |
| 28 | #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ |
| 29 | 0x18A0) |
| 30 | |
| 31 | #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) |
| 32 | #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) |
| 33 | #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) |
| 34 | #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) |
| 35 | |
| 36 | /* Generic Interrupt Controller Definitions */ |
| 37 | #define GICD_BASE 0x06000000 |
| 38 | #define GICR_BASE 0x06100000 |
| 39 | |
| 40 | /* SMMU Defintions */ |
| 41 | #define SMMU_BASE 0x05000000 /* GR0 Base */ |
| 42 | |
| 43 | /* DDR */ |
| 44 | #define CONFIG_SYS_FSL_DDR_LE |
| 45 | #define CONFIG_VERY_BIG_RAM |
| 46 | #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ |
| 47 | #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ |
| 48 | #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) |
| 49 | #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE |
| 50 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 |
| 51 | |
| 52 | |
| 53 | /* IFC */ |
| 54 | #define CONFIG_SYS_FSL_IFC_LE |
| 55 | |
| York Sun | 7b08d21 | 2014-06-23 15:15:56 -0700 | [diff] [blame^] | 56 | #ifdef CONFIG_LS2085A |
| York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 57 | #define CONFIG_MAX_CPUS 16 |
| 58 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
| 59 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 60 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } |
| 61 | #else |
| 62 | #error SoC not defined |
| 63 | #endif |
| 64 | |
| 65 | #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ |