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git01.mediatek.com / filogic / uboot / 7aba2553146c7b6532668ea4be1dfbb7180efe87 / . / arch / sandbox / dts / sandbox_pmic.dtsi
blob: 565c382ed45c2d83a1b423074eec069ed1ca25e6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]2/*
3 * Sandbox PMIC dts node
4 *
5 * Copyright (C) 2015 Samsung Electronics
6 * Przemyslaw Marczak <p.marczak@samsung.com>
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]7 */
8
9#include <dt-bindings/pmic/sandbox_pmic.h>
10
11&sandbox_pmic {
12 compatible = "sandbox,pmic";
13
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]14 buck1 {
15 regulator-name = "SUPPLY_1.2V";
16 regulator-min-microvolt = <1200000>;
17 regulator-max-microvolt = <1200000>;
18 regulator-min-microamp = <200000>;
19 regulator-max-microamp = <200000>;
20 regulator-always-on;
21 };
22
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]23 buck2: buck2 {
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]24 regulator-name = "SUPPLY_3.3V";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 };
28
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]29 ldo_1: ldo1 {
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]30 regulator-name = "VDD_EMMC_1.8V";
31 regulator-min-microvolt = <1800000>;
32 regulator-max-microvolt = <1800000>;
33 regulator-min-microamp = <100000>;
34 regulator-max-microamp = <100000>;
35 regulator-boot-on;
36 };
37
38 ldo2 {
39 regulator-name = "VDD_LCD_3.3V";
40 regulator-min-microvolt = <3300000>;
41 regulator-max-microvolt = <3300000>;
42 };
Felix Bracke23c3882017-11-27 09:14:16 +0100[diff] [blame]43
44 no_match_by_nodename {
45 regulator-name = "buck_SUPPLY_1.5V";
46 regulator-min-microvolt = <1500000>;
47 regulator-max-microvolt = <1500000>;
48 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]49};
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]50
51&mc34708 {
52 compatible = "fsl,mc34708";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]53};
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]54
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]55&i2c_emul {
56 emul_pmic0: pmic-emul0 {
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]57 compatible = "sandbox,i2c-pmic";
58
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]59 /*
60 * Default PMICs register values are set by macro
61 * VAL2REG(min, step, value) [uV/uA]
62 * VAL2OMREG(mode id)
63 * reg-defaults - byte array
64 */
65 reg-defaults = /bits/ 8 <
66 /* BUCK1 */
67 VAL2REG(800000, 25000, 1000000)
68 VAL2REG(150000, 25000, 150000)
69 VAL2OMREG(BUCK_OM_OFF)
70 /* BUCK2 */
71 VAL2REG(750000, 50000, 3000000)
72 VAL2REG(150000, 25000, 150000)
73 VAL2OMREG(0)
74 /* LDO1 */
75 VAL2REG(800000, 25000, 1600000)
76 VAL2REG(100000, 50000, 150000)
77 VAL2OMREG(LDO_OM_OFF)
78 /* LDO2 */
79 VAL2REG(750000, 50000, 3000000)
80 VAL2REG(150000, 25000, 150000)
81 VAL2OMREG(0)
82 /* reg[12:15] - not used */
83 0x00
84 0x00
85 0x00
86 0x00
87 >;
88 };
89
90 emul_pmic1: pmic-emul1 {
91 compatible = "sandbox,i2c-pmic";
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]92 reg-defaults = /bits/ 8 <
93 0x00 0x80 0x08 0xff 0xff 0xff 0x2e 0x01 0x08
94 0x40 0x80 0x81 0x5f 0xff 0xfb 0x1e 0x80 0x18
95 0x00 0x00 0x0e 0x00 0x00 0x14 0x00 0x00 0x00
96 0x00 0x00 0x20 0x00 0x01 0x3a 0x00 0x00 0x00
97 0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x00 0x00
98 0x42 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0x00
99 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x5f
100 0x01 0xff 0xff 0x00 0x00 0x00 0x00 0x7f 0xff
101 0x92 0x49 0x24 0x59 0x6d 0x34 0x18 0xc1 0x8c
102 0x00 0x60 0x18 0x51 0x48 0x45 0x14 0x51 0x45
103 0x00 0x06 0x32 0x00 0x00 0x00 0x06 0x9c 0x99
104 0x00 0x38 0x0a 0x00 0x38 0x0a 0x00 0x38 0x0a
105 0x00 0x38 0x0a 0x84 0x00 0x00 0x00 0x00 0x00
106 0x80 0x90 0x8f 0xf8 0x00 0x04 0x00 0x00 0x00
107 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
108 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
109 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
110 0x01 0x31 0x7e 0x2b 0x03 0xfd 0xc0 0x36 0x1b
111 0x60 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00
112 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
113 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
114 0x00 0x00 0x00
115 >;
116 };
117};