| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Kever Yang | 5db9e67 | 2017-06-23 16:11:05 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Rockchip Electronics Co., Ltd. |
| Kever Yang | 5db9e67 | 2017-06-23 16:11:05 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _ASM_ARCH_SDRAM_COMMON_H |
| 7 | #define _ASM_ARCH_SDRAM_COMMON_H |
| Jagan Teki | 3d401b2 | 2019-07-15 23:51:07 +0530 | [diff] [blame] | 8 | |
| Jagan Teki | 7ab369c | 2019-07-15 23:51:08 +0530 | [diff] [blame^] | 9 | enum { |
| 10 | DDR3 = 0x3, |
| 11 | LPDDR2 = 0x5, |
| 12 | LPDDR3 = 0x6, |
| 13 | LPDDR4 = 0x7, |
| 14 | UNUSED = 0xFF |
| 15 | }; |
| 16 | |
| Jagan Teki | 3d401b2 | 2019-07-15 23:51:07 +0530 | [diff] [blame] | 17 | struct sdram_cap_info { |
| 18 | unsigned int rank; |
| 19 | /* dram column number, 0 means this channel is invalid */ |
| 20 | unsigned int col; |
| 21 | /* dram bank number, 3:8bank, 2:4bank */ |
| 22 | unsigned int bk; |
| 23 | /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ |
| 24 | unsigned int bw; |
| 25 | /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ |
| 26 | unsigned int dbw; |
| 27 | /* |
| 28 | * row_3_4 = 1: 6Gb or 12Gb die |
| 29 | * row_3_4 = 0: normal die, power of 2 |
| 30 | */ |
| 31 | unsigned int row_3_4; |
| 32 | unsigned int cs0_row; |
| 33 | unsigned int cs1_row; |
| 34 | unsigned int ddrconfig; |
| 35 | }; |
| 36 | |
| 37 | struct sdram_base_params { |
| 38 | unsigned int ddr_freq; |
| 39 | unsigned int dramtype; |
| 40 | unsigned int num_channels; |
| 41 | unsigned int stride; |
| 42 | unsigned int odt; |
| 43 | }; |
| 44 | |
| Kever Yang | 5db9e67 | 2017-06-23 16:11:05 +0800 | [diff] [blame] | 45 | /* |
| 46 | * sys_reg bitfield struct |
| 47 | * [31] row_3_4_ch1 |
| 48 | * [30] row_3_4_ch0 |
| 49 | * [29:28] chinfo |
| 50 | * [27] rank_ch1 |
| 51 | * [26:25] col_ch1 |
| 52 | * [24] bk_ch1 |
| 53 | * [23:22] cs0_row_ch1 |
| 54 | * [21:20] cs1_row_ch1 |
| 55 | * [19:18] bw_ch1 |
| 56 | * [17:16] dbw_ch1; |
| 57 | * [15:13] ddrtype |
| 58 | * [12] channelnum |
| 59 | * [11] rank_ch0 |
| 60 | * [10:9] col_ch0 |
| 61 | * [8] bk_ch0 |
| 62 | * [7:6] cs0_row_ch0 |
| 63 | * [5:4] cs1_row_ch0 |
| 64 | * [3:2] bw_ch0 |
| 65 | * [1:0] dbw_ch0 |
| 66 | */ |
| 67 | #define SYS_REG_DDRTYPE_SHIFT 13 |
| 68 | #define SYS_REG_DDRTYPE_MASK 7 |
| 69 | #define SYS_REG_NUM_CH_SHIFT 12 |
| 70 | #define SYS_REG_NUM_CH_MASK 1 |
| 71 | #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) |
| 72 | #define SYS_REG_ROW_3_4_MASK 1 |
| 73 | #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) |
| 74 | #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) |
| 75 | #define SYS_REG_RANK_MASK 1 |
| 76 | #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) |
| 77 | #define SYS_REG_COL_MASK 3 |
| 78 | #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) |
| 79 | #define SYS_REG_BK_MASK 1 |
| 80 | #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) |
| 81 | #define SYS_REG_CS0_ROW_MASK 3 |
| 82 | #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) |
| 83 | #define SYS_REG_CS1_ROW_MASK 3 |
| 84 | #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) |
| 85 | #define SYS_REG_BW_MASK 3 |
| 86 | #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) |
| 87 | #define SYS_REG_DBW_MASK 3 |
| 88 | |
| 89 | /* Get sdram size decode from reg */ |
| 90 | size_t rockchip_sdram_size(phys_addr_t reg); |
| 91 | |
| 92 | /* Called by U-Boot board_init_r for Rockchip SoCs */ |
| 93 | int dram_init(void); |
| 94 | #endif |