Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
Jan Kiszka | ac31b5a | 2015-04-21 07:18:24 +0200 | [diff] [blame] | 9 | #ifndef CONFIG_ARMV7_NONSEC |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 10 | #error " Deep sleep needs non-secure mode support. " |
| 11 | #else |
| 12 | #include <asm/secure.h> |
| 13 | #endif |
| 14 | #include <asm/armv7.h> |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 15 | |
York Sun | c4f047c | 2017-03-27 11:41:03 -0700 | [diff] [blame] | 16 | #if defined(CONFIG_ARCH_LS1021A) |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 17 | #include <asm/arch/immap_ls102xa.h> |
| 18 | #endif |
| 19 | |
| 20 | #include "sleep.h" |
Zhao Qiang | e75fc44 | 2015-04-07 15:09:54 +0800 | [diff] [blame] | 21 | #ifdef CONFIG_U_QE |
Qianyu Gong | ae6a758 | 2016-02-18 13:01:59 +0800 | [diff] [blame] | 22 | #include <fsl_qe.h> |
Zhao Qiang | e75fc44 | 2015-04-07 15:09:54 +0800 | [diff] [blame] | 23 | #endif |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 24 | |
| 25 | DECLARE_GLOBAL_DATA_PTR; |
| 26 | |
| 27 | void __weak board_mem_sleep_setup(void) |
| 28 | { |
| 29 | } |
| 30 | |
| 31 | void __weak board_sleep_prepare(void) |
| 32 | { |
| 33 | } |
| 34 | |
| 35 | bool is_warm_boot(void) |
| 36 | { |
| 37 | struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
| 38 | |
| 39 | if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) |
| 40 | return 1; |
| 41 | |
| 42 | return 0; |
| 43 | } |
| 44 | |
| 45 | void fsl_dp_disable_console(void) |
| 46 | { |
| 47 | gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; |
| 48 | } |
| 49 | |
| 50 | /* |
| 51 | * When wakeup from deep sleep, the first 128 bytes space |
| 52 | * will be used to do DDR training which corrupts the data |
| 53 | * in there. This function will restore them. |
| 54 | */ |
| 55 | static void dp_ddr_restore(void) |
| 56 | { |
| 57 | u64 *src, *dst; |
| 58 | int i; |
| 59 | struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; |
| 60 | |
| 61 | /* get the address of ddr date from SPARECR3 */ |
| 62 | src = (u64 *)in_le32(&scfg->sparecr[2]); |
| 63 | dst = (u64 *)CONFIG_SYS_SDRAM_BASE; |
| 64 | |
| 65 | for (i = 0; i < DDR_BUFF_LEN / 8; i++) |
| 66 | *dst++ = *src++; |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 67 | } |
| 68 | |
York Sun | c4f047c | 2017-03-27 11:41:03 -0700 | [diff] [blame] | 69 | #if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) |
Hongbo Zhang | 539e4f1 | 2016-08-19 17:20:33 +0800 | [diff] [blame] | 70 | void ls1_psci_resume_fixup(void) |
| 71 | { |
| 72 | u32 tmp; |
| 73 | struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; |
| 74 | |
| 75 | #ifdef QIXIS_BASE |
| 76 | void *qixis_base = (void *)QIXIS_BASE; |
| 77 | |
| 78 | /* Pull on PCIe RST# */ |
| 79 | out_8(qixis_base + QIXIS_RST_FORCE_3, 0); |
| 80 | |
| 81 | /* disable deep sleep signals in FPGA */ |
| 82 | tmp = in_8(qixis_base + QIXIS_PWR_CTL2); |
| 83 | tmp &= ~QIXIS_PWR_CTL2_PCTL; |
| 84 | out_8(qixis_base + QIXIS_PWR_CTL2, tmp); |
| 85 | #endif |
| 86 | |
| 87 | /* Disable wakeup interrupt during deep sleep */ |
| 88 | out_be32(&scfg->pmcintecr, 0); |
| 89 | /* Clear PMC interrupt status */ |
| 90 | out_be32(&scfg->pmcintsr, 0xffffffff); |
| 91 | |
| 92 | /* Disable Warm Device Reset */ |
| 93 | tmp = in_be32(&scfg->dpslpcr); |
| 94 | tmp &= ~SCFG_DPSLPCR_WDRR_EN; |
| 95 | out_be32(&scfg->dpslpcr, tmp); |
| 96 | } |
| 97 | #endif |
| 98 | |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 99 | static void dp_resume_prepare(void) |
| 100 | { |
| 101 | dp_ddr_restore(); |
| 102 | board_sleep_prepare(); |
| 103 | armv7_init_nonsec(); |
Zhao Qiang | e75fc44 | 2015-04-07 15:09:54 +0800 | [diff] [blame] | 104 | #ifdef CONFIG_U_QE |
| 105 | u_qe_resume(); |
| 106 | #endif |
York Sun | c4f047c | 2017-03-27 11:41:03 -0700 | [diff] [blame] | 107 | #if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) |
Hongbo Zhang | 539e4f1 | 2016-08-19 17:20:33 +0800 | [diff] [blame] | 108 | ls1_psci_resume_fixup(); |
| 109 | #endif |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | int fsl_dp_resume(void) |
| 113 | { |
| 114 | u32 start_addr; |
| 115 | void (*kernel_resume)(void); |
| 116 | struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; |
| 117 | |
| 118 | if (!is_warm_boot()) |
| 119 | return 0; |
| 120 | |
| 121 | dp_resume_prepare(); |
| 122 | |
| 123 | /* Get the entry address and jump to kernel */ |
Hongbo Zhang | 539e4f1 | 2016-08-19 17:20:33 +0800 | [diff] [blame] | 124 | start_addr = in_le32(&scfg->sparecr[3]); |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 125 | debug("Entry address is 0x%08x\n", start_addr); |
| 126 | kernel_resume = (void (*)(void))start_addr; |
| 127 | secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); |
| 128 | |
| 129 | return 0; |
| 130 | } |