| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010 |
| 4 | * Texas Instruments Incorporated, <www.ti.com> |
| 5 | * |
| SRICHARAN R | 359824e | 2012-03-12 02:25:35 +0000 | [diff] [blame] | 6 | * Sricharan R <r.sricharan@ti.com> |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 7 | */ |
| 8 | #ifndef _EVM5430_MUX_DATA_H |
| 9 | #define _EVM5430_MUX_DATA_H |
| 10 | |
| 11 | #include <asm/arch/mux_omap5.h> |
| 12 | |
| 13 | const struct pad_conf_entry core_padconf_array_essential[] = { |
| 14 | |
| SRICHARAN R | 359824e | 2012-03-12 02:25:35 +0000 | [diff] [blame] | 15 | {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */ |
| 16 | {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */ |
| 17 | {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */ |
| 18 | {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */ |
| 19 | {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */ |
| 20 | {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */ |
| 21 | {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */ |
| 22 | {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */ |
| 23 | {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */ |
| 24 | {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */ |
| 25 | {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */ |
| 26 | {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */ |
| 27 | {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/ |
| 28 | {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/ |
| 29 | {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/ |
| 30 | {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/ |
| 31 | {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */ |
| 32 | {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */ |
| SRICHARAN R | 264a06c | 2012-06-12 19:53:32 +0000 | [diff] [blame] | 33 | {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ |
| 34 | {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ |
| 35 | {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ |
| 36 | {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ |
| 37 | {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ |
| 38 | {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ |
| 39 | {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ |
| 40 | {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ |
| 41 | {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ |
| Dan Murphy | 05d5f99 | 2013-07-11 13:10:28 -0500 | [diff] [blame] | 42 | {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ |
| 43 | {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ |
| Dan Murphy | 29d04b5 | 2013-08-01 14:05:59 -0500 | [diff] [blame] | 44 | {HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */ |
| 45 | {HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */ |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | const struct pad_conf_entry wkup_padconf_array_essential[] = { |
| 49 | |
| SRICHARAN R | 359824e | 2012-03-12 02:25:35 +0000 | [diff] [blame] | 50 | {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ |
| 51 | {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ |
| 52 | {SYS_32K, (IEN | M0)}, /* SYS_32K */ |
| Dan Murphy | 29d04b5 | 2013-08-01 14:05:59 -0500 | [diff] [blame] | 53 | {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */ |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 54 | |
| 55 | }; |
| 56 | |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 57 | #endif /* _EVM4430_MUX_DATA_H */ |