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git01.mediatek.com / filogic / uboot / 7a25c30461a65de84a2dda72e47c5bfc0033c2dc / . / drivers / dma / ti / k3-psil-j784s4.c
blob: 7f06a1f307cbe78bbd5bf8c6e6f5433ec8c75d32 [file] [log] [blame]
Apurva Nandan7a25c302024-02-24 01:51:45 +0530[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com
4 */
5#include <linux/kernel.h>
6
7#include "k3-psil-priv.h"
8
9#define PSIL_PDMA_XY_TR(x) \
10 { \
11 .thread_id = x, \
12 .ep_config = { \
13 .ep_type = PSIL_EP_PDMA_XY, \
14 }, \
15 }
16
17#define PSIL_PDMA_XY_PKT(x) \
18 { \
19 .thread_id = x, \
20 .ep_config = { \
21 .ep_type = PSIL_EP_PDMA_XY, \
22 .pkt_mode = 1, \
23 }, \
24 }
25
26#define PSIL_PDMA_MCASP(x) \
27 { \
28 .thread_id = x, \
29 .ep_config = { \
30 .ep_type = PSIL_EP_PDMA_XY, \
31 .pdma_acc32 = 1, \
32 .pdma_burst = 1, \
33 }, \
34 }
35
36#define PSIL_ETHERNET(x) \
37 { \
38 .thread_id = x, \
39 .ep_config = { \
40 .ep_type = PSIL_EP_NATIVE, \
41 .pkt_mode = 1, \
42 .needs_epib = 1, \
43 .psd_size = 16, \
44 }, \
45 }
46
47#define PSIL_SA2UL(x, tx) \
48 { \
49 .thread_id = x, \
50 .ep_config = { \
51 .ep_type = PSIL_EP_NATIVE, \
52 .pkt_mode = 1, \
53 .needs_epib = 1, \
54 .psd_size = 64, \
55 .notdpkt = tx, \
56 }, \
57 }
58
59/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
60static struct psil_ep j784s4_src_ep_map[] = {
61 /* PDMA_MCASP - McASP0-4 */
62 PSIL_PDMA_MCASP(0x4400),
63 PSIL_PDMA_MCASP(0x4401),
64 PSIL_PDMA_MCASP(0x4402),
65 PSIL_PDMA_MCASP(0x4403),
66 PSIL_PDMA_MCASP(0x4404),
67 /* PDMA_SPI_G0 - SPI0-3 */
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
75 PSIL_PDMA_XY_PKT(0x4607),
76 PSIL_PDMA_XY_PKT(0x4608),
77 PSIL_PDMA_XY_PKT(0x4609),
78 PSIL_PDMA_XY_PKT(0x460a),
79 PSIL_PDMA_XY_PKT(0x460b),
80 PSIL_PDMA_XY_PKT(0x460c),
81 PSIL_PDMA_XY_PKT(0x460d),
82 PSIL_PDMA_XY_PKT(0x460e),
83 PSIL_PDMA_XY_PKT(0x460f),
84 /* PDMA_SPI_G1 - SPI4-7 */
85 PSIL_PDMA_XY_PKT(0x4610),
86 PSIL_PDMA_XY_PKT(0x4611),
87 PSIL_PDMA_XY_PKT(0x4612),
88 PSIL_PDMA_XY_PKT(0x4613),
89 PSIL_PDMA_XY_PKT(0x4614),
90 PSIL_PDMA_XY_PKT(0x4615),
91 PSIL_PDMA_XY_PKT(0x4616),
92 PSIL_PDMA_XY_PKT(0x4617),
93 PSIL_PDMA_XY_PKT(0x4618),
94 PSIL_PDMA_XY_PKT(0x4619),
95 PSIL_PDMA_XY_PKT(0x461a),
96 PSIL_PDMA_XY_PKT(0x461b),
97 PSIL_PDMA_XY_PKT(0x461c),
98 PSIL_PDMA_XY_PKT(0x461d),
99 PSIL_PDMA_XY_PKT(0x461e),
100 PSIL_PDMA_XY_PKT(0x461f),
101 /* PDMA_USART_G0 - UART0-1 */
102 PSIL_PDMA_XY_PKT(0x4700),
103 PSIL_PDMA_XY_PKT(0x4701),
104 /* PDMA_USART_G1 - UART2-3 */
105 PSIL_PDMA_XY_PKT(0x4702),
106 PSIL_PDMA_XY_PKT(0x4703),
107 /* PDMA_USART_G2 - UART4-9 */
108 PSIL_PDMA_XY_PKT(0x4704),
109 PSIL_PDMA_XY_PKT(0x4705),
110 PSIL_PDMA_XY_PKT(0x4706),
111 PSIL_PDMA_XY_PKT(0x4707),
112 PSIL_PDMA_XY_PKT(0x4708),
113 PSIL_PDMA_XY_PKT(0x4709),
114 /* CPSW0 */
115 PSIL_ETHERNET(0x7000),
116 /* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
117 PSIL_PDMA_XY_PKT(0x7100),
118 PSIL_PDMA_XY_PKT(0x7101),
119 PSIL_PDMA_XY_PKT(0x7102),
120 PSIL_PDMA_XY_PKT(0x7103),
121 /* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
122 PSIL_PDMA_XY_PKT(0x7200),
123 PSIL_PDMA_XY_PKT(0x7201),
124 PSIL_PDMA_XY_PKT(0x7202),
125 PSIL_PDMA_XY_PKT(0x7203),
126 PSIL_PDMA_XY_PKT(0x7204),
127 PSIL_PDMA_XY_PKT(0x7205),
128 PSIL_PDMA_XY_PKT(0x7206),
129 PSIL_PDMA_XY_PKT(0x7207),
130 /* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
131 PSIL_PDMA_XY_PKT(0x7300),
132 /* MCU_PDMA_ADC - ADC0-1 */
133 PSIL_PDMA_XY_TR(0x7400),
134 PSIL_PDMA_XY_TR(0x7401),
135 PSIL_PDMA_XY_TR(0x7402),
136 PSIL_PDMA_XY_TR(0x7403),
137 /* SA2UL */
138 PSIL_SA2UL(0x7500, 0),
139 PSIL_SA2UL(0x7501, 0),
140 PSIL_SA2UL(0x7502, 0),
141 PSIL_SA2UL(0x7503, 0),
142};
143
144/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
145static struct psil_ep j784s4_dst_ep_map[] = {
146 /* CPSW0 */
147 PSIL_ETHERNET(0xf000),
148 PSIL_ETHERNET(0xf001),
149 PSIL_ETHERNET(0xf002),
150 PSIL_ETHERNET(0xf003),
151 PSIL_ETHERNET(0xf004),
152 PSIL_ETHERNET(0xf005),
153 PSIL_ETHERNET(0xf006),
154 PSIL_ETHERNET(0xf007),
155 /* SA2UL */
156 PSIL_SA2UL(0xf500, 1),
157 PSIL_SA2UL(0xf501, 1),
158};
159
160struct psil_ep_map j784s4_ep_map = {
161 .name = "j784s4",
162 .src = j784s4_src_ep_map,
163 .src_count = ARRAY_SIZE(j784s4_src_ep_map),
164 .dst = j784s4_dst_ep_map,
165 .dst_count = ARRAY_SIZE(j784s4_dst_ep_map),
166};