| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm IPQ8074 TLMM pin controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Bjorn Andersson <andersson@kernel.org> |
| 11 | - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
| 12 | |
| 13 | description: |
| 14 | Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC. |
| 15 | |
| 16 | properties: |
| 17 | compatible: |
| 18 | const: qcom,ipq8074-pinctrl |
| 19 | |
| 20 | reg: |
| 21 | maxItems: 1 |
| 22 | |
| 23 | interrupts: |
| 24 | maxItems: 1 |
| 25 | |
| 26 | interrupt-controller: true |
| 27 | "#interrupt-cells": true |
| 28 | gpio-controller: true |
| 29 | "#gpio-cells": true |
| 30 | gpio-ranges: true |
| 31 | wakeup-parent: true |
| 32 | |
| 33 | gpio-reserved-ranges: |
| 34 | minItems: 1 |
| 35 | maxItems: 35 |
| 36 | |
| 37 | gpio-line-names: |
| 38 | maxItems: 70 |
| 39 | |
| 40 | patternProperties: |
| 41 | "-state$": |
| 42 | oneOf: |
| 43 | - $ref: "#/$defs/qcom-ipq8074-tlmm-state" |
| 44 | - patternProperties: |
| 45 | "-pins$": |
| 46 | $ref: "#/$defs/qcom-ipq8074-tlmm-state" |
| 47 | additionalProperties: false |
| 48 | |
| 49 | $defs: |
| 50 | qcom-ipq8074-tlmm-state: |
| 51 | type: object |
| 52 | description: |
| 53 | Pinctrl node's client devices use subnodes for desired pin configuration. |
| 54 | Client device subnodes use below standard properties. |
| 55 | $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state |
| 56 | unevaluatedProperties: false |
| 57 | |
| 58 | properties: |
| 59 | pins: |
| 60 | description: |
| 61 | List of gpio pins affected by the properties specified in this |
| 62 | subnode. |
| 63 | items: |
| 64 | pattern: "^gpio([0-9]|[1-6][0-9]|70)$" |
| 65 | minItems: 1 |
| 66 | maxItems: 36 |
| 67 | |
| 68 | function: |
| 69 | description: |
| 70 | Specify the alternative function to be configured for the specified |
| 71 | pins. |
| 72 | |
| 73 | enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2, |
| 74 | atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync, |
| 75 | audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync, |
| 76 | audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c, |
| 77 | blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart, |
| 78 | blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2, |
| 79 | blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0, |
| 80 | blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi, |
| 81 | blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, cxc0, |
| 82 | cxc1, dbg_out, gcc_plltest, gcc_tlmm, ldo_en, ldo_update, led0, |
| 83 | led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, mac1_sa1, mac1_sa2, |
| 84 | mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst, |
| 85 | pcie0_wake, pcie1_clk, pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, |
| 86 | pcm_fsync, pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, |
| 87 | pta1_1, pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3, |
| 88 | qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, |
| 89 | qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, |
| 90 | qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, |
| 91 | qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, |
| 92 | qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, |
| 93 | qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write, |
| 94 | tsens_max, wci2a, wci2b, wci2c, wci2d ] |
| 95 | |
| 96 | required: |
| 97 | - pins |
| 98 | |
| 99 | allOf: |
| 100 | - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# |
| 101 | |
| 102 | required: |
| 103 | - compatible |
| 104 | - reg |
| 105 | |
| 106 | additionalProperties: false |
| 107 | |
| 108 | examples: |
| 109 | - | |
| 110 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 111 | |
| 112 | tlmm: pinctrl@1000000 { |
| 113 | compatible = "qcom,ipq8074-pinctrl"; |
| 114 | reg = <0x01000000 0x300000>; |
| 115 | gpio-controller; |
| 116 | #gpio-cells = <0x2>; |
| 117 | gpio-ranges = <&tlmm 0 0 70>; |
| 118 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| 119 | interrupt-controller; |
| 120 | #interrupt-cells = <0x2>; |
| 121 | |
| 122 | serial4-state { |
| 123 | pins = "gpio23", "gpio24"; |
| 124 | function = "blsp4_uart1"; |
| 125 | drive-strength = <8>; |
| 126 | bias-disable; |
| 127 | }; |
| 128 | }; |