| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | Cirrus Logic CLPS711X Interrupt Controller |
| 2 | |
| 3 | Required properties: |
| 4 | |
| 5 | - compatible: Should be "cirrus,ep7209-intc". |
| 6 | - reg: Specifies base physical address of the registers set. |
| 7 | - interrupt-controller: Identifies the node as an interrupt controller. |
| 8 | - #interrupt-cells: Specifies the number of cells needed to encode an |
| 9 | interrupt source. The value shall be 1. |
| 10 | |
| 11 | The interrupt sources are as follows: |
| 12 | ID Name Description |
| 13 | --------------------------- |
| 14 | 1: BLINT Battery low (FIQ) |
| 15 | 3: MCINT Media changed (FIQ) |
| 16 | 4: CSINT CODEC sound |
| 17 | 5: EINT1 External 1 |
| 18 | 6: EINT2 External 2 |
| 19 | 7: EINT3 External 3 |
| 20 | 8: TC1OI TC1 under flow |
| 21 | 9: TC2OI TC2 under flow |
| 22 | 10: RTCMI RTC compare match |
| 23 | 11: TINT 64Hz tick |
| 24 | 12: UTXINT1 UART1 transmit FIFO half empty |
| 25 | 13: URXINT1 UART1 receive FIFO half full |
| 26 | 14: UMSINT UART1 modem status changed |
| 27 | 15: SSEOTI SSI1 end of transfer |
| 28 | 16: KBDINT Keyboard |
| 29 | 17: SS2RX SSI2 receive FIFO half or greater full |
| 30 | 18: SS2TX SSI2 transmit FIFO less than half empty |
| 31 | 28: UTXINT2 UART2 transmit FIFO half empty |
| 32 | 29: URXINT2 UART2 receive FIFO half full |
| 33 | 32: DAIINT DAI interface (FIQ) |
| 34 | |
| 35 | Example: |
| 36 | intc: interrupt-controller { |
| 37 | compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; |
| 38 | reg = <0x80000000 0x4000>; |
| 39 | interrupt-controller; |
| 40 | #interrupt-cells = <1>; |
| 41 | }; |