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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Klaus Goger81039932017-04-07 19:13:38 +02002/*
3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
Klaus Goger81039932017-04-07 19:13:38 +02004 */
Philipp Tomsich3df66262017-09-29 19:27:54 +02005
Klaus Goger81039932017-04-07 19:13:38 +02006#include <dm.h>
Jakob Unterwurzacherb0720632017-12-15 16:23:14 +01007#include <syscon.h>
Klaus Goger81039932017-04-07 19:13:38 +02008#include <dm/pinctrl.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +08009#include <asm/arch-rockchip/clock.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080010#include <asm/arch-rockchip/hardware.h>
11#include <asm/arch-rockchip/grf_rk3399.h>
Quentin Schulz1e1a92b2024-01-17 18:59:10 +010012#include "../common/common.h"
Klaus Goger81039932017-04-07 19:13:38 +020013
Jakob Unterwurzacherb0720632017-12-15 16:23:14 +010014static void setup_iodomain(void)
15{
16 const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3;
17 struct rk3399_grf_regs *grf =
18 syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
19
20 /*
21 * Set bit 3 in GRF_IO_VSEL so PCIE_RST# works (pin GPIO4_C6).
22 * Linux assumes that PCIE_RST# works out of the box as it probes
23 * PCIe before loading the iodomain driver.
24 */
25 rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT);
26}
27
Quentin Schulz14186252024-03-11 13:01:50 +010028int rockchip_early_misc_init_r(void)
Philipp Tomsich2ebe2892017-05-05 19:21:39 +020029{
Jakob Unterwurzacherb0720632017-12-15 16:23:14 +010030 setup_iodomain();
Klaus Goger810182f2018-05-24 17:15:53 +020031 setup_boottargets();
Philipp Tomsich2ebe2892017-05-05 19:21:39 +020032
33 return 0;
34}