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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Saket Sinha331141a2015-08-22 12:20:55 +05302/*
3 * Based on acpi.c from coreboot
4 *
5 * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
Bin Mengbbcff8d2016-05-07 07:46:22 -07006 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
Saket Sinha331141a2015-08-22 12:20:55 +05307 */
8
Bin Meng3f047072018-07-18 21:42:17 -07009#ifndef __ASM_ACPI_TABLE_H__
10#define __ASM_ACPI_TABLE_H__
11
Simon Glassf4112b02020-09-22 12:45:30 -060012#ifndef __ACPI__
13
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <pci.h>
15
Simon Glass858fed12020-04-08 16:57:36 -060016struct acpi_facs;
17struct acpi_fadt;
Bin Mengd9050c62016-06-17 02:13:16 -070018struct acpi_global_nvs;
Simon Glass858fed12020-04-08 16:57:36 -060019struct acpi_madt_ioapic;
20struct acpi_madt_irqoverride;
21struct acpi_madt_lapic_nmi;
22struct acpi_mcfg_mmconfig;
23struct acpi_table_header;
Andy Shevchenko6e84f0872018-11-20 23:52:37 +020024
Saket Sinha331141a2015-08-22 12:20:55 +053025/* These can be used by the target port */
26
Bin Meng3c5234e2016-05-07 07:46:30 -070027int acpi_create_madt_lapics(u32 current);
Bin Meng44256b02016-05-07 07:46:25 -070028int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
29 u32 addr, u32 gsi_base);
Saket Sinha331141a2015-08-22 12:20:55 +053030int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
Bin Meng44256b02016-05-07 07:46:25 -070031 u8 bus, u8 source, u32 gsirq, u16 flags);
32int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
33 u8 cpu, u16 flags, u8 lint);
Bin Menga1ec7db2016-05-07 07:46:26 -070034u32 acpi_fill_madt(u32 current);
Andy Shevchenkoc1ae9802017-07-21 22:32:05 +030035int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
36 u16 seg_nr, u8 start, u8 end);
Simon Glass9ed41e72020-07-07 21:32:05 -060037
38/**
Simon Glass4ffe8b02020-09-22 12:45:09 -060039 * acpi_write_hpet() - Write out a HPET table
40 *
41 * Write out the table for High-Precision Event Timers
42 *
43 * @ctx: Current ACPI context
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010044 * Return: 0 if OK, -ve on error
Simon Glass4ffe8b02020-09-22 12:45:09 -060045 */
46int acpi_write_hpet(struct acpi_ctx *ctx);
47
48/**
Simon Glass95971892020-09-22 12:45:10 -060049 * acpi_write_dbg2_pci_uart() - Write out a DBG2 table
50 *
51 * @ctx: Current ACPI context
52 * @dev: Debug UART device to describe
53 * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010054 * Return: 0 if OK, -ve on error
Simon Glass95971892020-09-22 12:45:10 -060055 */
56int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
57 uint access_size);
58
59/**
Simon Glass9ed41e72020-07-07 21:32:05 -060060 * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
61 *
62 * @gnvs: Table to fill in
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010063 * Return: 0 if OK, -ve on error
Simon Glass9ed41e72020-07-07 21:32:05 -060064 */
65int acpi_create_gnvs(struct acpi_global_nvs *gnvs);
66
Bin Meng34bc74a2017-04-21 07:24:36 -070067/**
Simon Glassd73344b2020-09-22 12:45:14 -060068 * arch_read_sci_irq_select() - Read the system-control interrupt number
69 *
70 * @returns value of IRQ register in the PMC
71 */
72int arch_read_sci_irq_select(void);
73
74/**
75 * arch_write_sci_irq_select() - Set the system-control interrupt number
76 *
77 * @scis: New value for IRQ register in the PMC
78 */
79int arch_write_sci_irq_select(uint scis);
80
81/**
82 * arch_madt_sci_irq_polarity() - Return the priority to use for the MADT
83 *
84 * @sci: System-control interrupt number
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010085 * Return: priority to use (MP_IRQ_POLARITY_...)
Simon Glassd73344b2020-09-22 12:45:14 -060086 */
87int arch_madt_sci_irq_polarity(int sci);
88
Simon Glass87cf8d22020-09-22 12:45:16 -060089/**
90 * acpi_create_dmar_drhd() - Create a table for DMA remapping with the IOMMU
91 *
92 * See here for the specification
93 * https://software.intel.com/sites/default/files/managed/c5/15/vt-directed-io-spec.pdf
94 *
95 * @ctx: ACPI context pointer
96 * @flags: (DRHD_INCLUDE_...)
97 * @segment: PCI segment asscociated with this unit
98 * @bar: Base address of remapping hardware register-set for this unit
99 */
100void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
101 u64 bar);
102
103/**
104 * acpi_create_dmar_rmrr() - Set up an RMRR
105 *
106 * This sets up a Reserved-Memory Region Reporting structure, used to allow
107 * DMA to regions used by devices that the BIOS controls.
108 *
109 * @ctx: ACPI context pointer
110 * @segment: PCI segment asscociated with this unit
111 * @bar: Base address of mapping
112 * @limit: End address of mapping
113 */
114void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar,
115 u64 limit);
116
117/**
118 * acpi_dmar_drhd_fixup() - Set the length of an DRHD
119 *
120 * This sets the DRHD length field based on the current ctx->current
121 *
122 * @ctx: ACPI context pointer
123 * @base: Address of the start of the DRHD
124 */
125void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base);
126
127/**
128 * acpi_dmar_rmrr_fixup() - Set the length of an RMRR
129 *
130 * This sets the RMRR length field based on the current ctx->current
131 *
132 * @ctx: ACPI context pointer
133 * @base: Address of the start of the RMRR
134 */
135void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base);
136
137/**
138 * acpi_create_dmar_ds_pci() - Set up a DMAR scope for a PCI device
139 *
140 * @ctx: ACPI context pointer
141 * @bdf: PCI device to add
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100142 * Return: length of mapping in bytes
Simon Glass87cf8d22020-09-22 12:45:16 -0600143 */
144int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf);
145
146/**
147 * acpi_create_dmar_ds_pci_br() - Set up a DMAR scope for a PCI bridge
148 *
149 * This is used to provide a mapping for a PCI bridge
150 *
151 * @ctx: ACPI context pointer
152 * @bdf: PCI device to add
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100153 * Return: length of mapping in bytes
Simon Glass87cf8d22020-09-22 12:45:16 -0600154 */
155int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf);
156
157/**
158 * acpi_create_dmar_ds_ioapic() - Set up a DMAR scope for an IOAPIC device
159 *
160 * @ctx: ACPI context pointer
161 * @enumeration_id: Enumeration ID (typically 2)
162 * @bdf: PCI device to add
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100163 * Return: length of mapping in bytes
Simon Glass87cf8d22020-09-22 12:45:16 -0600164 */
165int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id,
166 pci_dev_t bdf);
167
168/**
169 * acpi_create_dmar_ds_msi_hpet() - Set up a DMAR scope for an HPET
170 *
171 * Sets up a scope for a High-Precision Event Timer that supports
172 * Message-Signalled Interrupts
173 *
174 * @ctx: ACPI context pointer
175 * @enumeration_id: Enumeration ID (typically 0)
176 * @bdf: PCI device to add
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100177 * Return: length of mapping in bytes
Simon Glass87cf8d22020-09-22 12:45:16 -0600178 */
179int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id,
180 pci_dev_t bdf);
181
182/**
183 * acpi_fadt_common() - Handle common parts of filling out an FADT
184 *
185 * This sets up the Fixed ACPI Description Table
186 *
187 * @fadt: Pointer to place to put FADT
188 * @facs: Pointer to the FACS
189 * @dsdt: Pointer to the DSDT
190 */
191void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
192 void *dsdt);
193
194/**
195 * intel_acpi_fill_fadt() - Set up the contents of the FADT
196 *
197 * This sets up parts of the Fixed ACPI Description Table that are common to
198 * Intel chips
199 *
200 * @fadt: Pointer to place to put FADT
201 */
202void intel_acpi_fill_fadt(struct acpi_fadt *fadt);
203
Simon Glassf4112b02020-09-22 12:45:30 -0600204#endif /* !__ACPI__ */
205
Bin Meng3f047072018-07-18 21:42:17 -0700206#endif /* __ASM_ACPI_TABLE_H__ */