blob: 0adbb8df3c2ca8c0c553996902926abe57bd0f54 [file] [log] [blame]
Mario Six8862f452018-10-04 09:00:54 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
5 */
6
Mario Six8862f452018-10-04 09:00:54 +02007#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Mario Six8862f452018-10-04 09:00:54 +02009#include <dm/lists.h>
10
11#include "gdsys_soc.h"
12
13/**
14 * struct gdsys_soc_priv - Private data for gdsys soc bus
15 * @fpga: The gdsys IHS FPGA this bus is associated with
16 */
17struct gdsys_soc_priv {
18 struct udevice *fpga;
19};
20
21static const struct udevice_id gdsys_soc_ids[] = {
22 { .compatible = "gdsys,soc" },
23 { /* sentinel */ }
24};
25
26int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga)
27{
28 struct gdsys_soc_priv *bus_priv;
29
30 if (!child->parent) {
31 debug("%s: Invalid parent\n", child->name);
32 return -EINVAL;
33 }
34
35 if (!device_is_compatible(child->parent, "gdsys,soc")) {
36 debug("%s: Not child of a gdsys soc\n", child->name);
37 return -EINVAL;
38 }
39
40 bus_priv = dev_get_priv(child->parent);
41
42 *fpga = bus_priv->fpga;
43
44 return 0;
45}
46
47static int gdsys_soc_probe(struct udevice *dev)
48{
49 struct gdsys_soc_priv *priv = dev_get_priv(dev);
50 struct udevice *fpga;
51 int res = uclass_get_device_by_phandle(UCLASS_MISC, dev, "fpga",
52 &fpga);
53 if (res == -ENOENT) {
54 debug("%s: Could not find 'fpga' phandle\n", dev->name);
55 return -EINVAL;
56 }
57
58 if (res == -ENODEV) {
59 debug("%s: Could not get FPGA device\n", dev->name);
60 return -EINVAL;
61 }
62
63 priv->fpga = fpga;
64
65 return 0;
66}
67
68U_BOOT_DRIVER(gdsys_soc_bus) = {
69 .name = "gdsys_soc_bus",
70 .id = UCLASS_SIMPLE_BUS,
71 .of_match = gdsys_soc_ids,
72 .probe = gdsys_soc_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -070073 .priv_auto = sizeof(struct gdsys_soc_priv),
Mario Six8862f452018-10-04 09:00:54 +020074};