Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 2 | /* |
chenhui zhao | 701a8e4 | 2011-09-15 14:52:34 +0800 | [diff] [blame] | 3 | * Copyright 2004, 2011 Freescale Semiconductor. |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 6 | #include <config.h> |
Tom Rini | 8c70baa | 2021-12-14 13:36:40 -0500 | [diff] [blame] | 7 | #include <clock_legacy.h> |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 8 | #include <linux/types.h> |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 9 | |
| 10 | /* |
| 11 | * CADMUS Board System Registers |
| 12 | */ |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 13 | #ifndef CFG_SYS_CADMUS_BASE_REG |
| 14 | #define CFG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 15 | #endif |
| 16 | |
| 17 | typedef struct cadmus_reg { |
| 18 | u_char cm_ver; /* Board version */ |
| 19 | u_char cm_csr; /* General control/status */ |
| 20 | u_char cm_rst; /* Reset control */ |
| 21 | u_char cm_hsclk; /* High speed clock */ |
| 22 | u_char cm_hsxclk; /* High speed clock extended */ |
| 23 | u_char cm_led; /* LED data */ |
| 24 | u_char cm_pci; /* PCI control/status */ |
| 25 | u_char cm_dma; /* DMA control */ |
| 26 | u_char cm_reserved[248]; /* Total 256 bytes */ |
| 27 | } cadmus_reg_t; |
| 28 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 29 | unsigned int |
| 30 | get_board_version(void) |
| 31 | { |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 32 | volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 33 | |
| 34 | return cadmus->cm_ver; |
| 35 | } |
| 36 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 37 | unsigned long |
Tom Rini | aea2a99 | 2021-12-14 13:36:39 -0500 | [diff] [blame] | 38 | get_board_sys_clk(void) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 39 | { |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 40 | volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 41 | |
| 42 | uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ |
| 43 | |
| 44 | if (pci1_speed == 0) { |
chenhui zhao | 701a8e4 | 2011-09-15 14:52:34 +0800 | [diff] [blame] | 45 | return 33333333; |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 46 | } else if (pci1_speed == 1) { |
chenhui zhao | 701a8e4 | 2011-09-15 14:52:34 +0800 | [diff] [blame] | 47 | return 66666666; |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 48 | } else { |
| 49 | /* Really, unknown. Be safe? */ |
chenhui zhao | 701a8e4 | 2011-09-15 14:52:34 +0800 | [diff] [blame] | 50 | return 33333333; |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 51 | } |
| 52 | } |
| 53 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 54 | unsigned int |
| 55 | get_pci_slot(void) |
| 56 | { |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 57 | volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 58 | |
| 59 | /* |
| 60 | * PCI slot in USER bits CSR[6:7] by convention. |
| 61 | */ |
| 62 | return ((cadmus->cm_csr >> 6) & 0x3) + 1; |
| 63 | } |
| 64 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 65 | unsigned int |
| 66 | get_pci_dual(void) |
| 67 | { |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 68 | volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 69 | |
| 70 | /* |
| 71 | * PCI DUAL in CM_PCI[3] |
| 72 | */ |
| 73 | return cadmus->cm_pci & 0x10; |
| 74 | } |