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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk0aeb8532004-10-10 21:21:55 +00002/*
chenhui zhao701a8e42011-09-15 14:52:34 +08003 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk0aeb8532004-10-10 21:21:55 +00004 */
5
Tom Rinidec7ea02024-05-20 13:35:03 -06006#include <config.h>
Tom Rini8c70baa2021-12-14 13:36:40 -05007#include <clock_legacy.h>
Tom Rinidec7ea02024-05-20 13:35:03 -06008#include <linux/types.h>
wdenk0aeb8532004-10-10 21:21:55 +00009
10/*
11 * CADMUS Board System Registers
12 */
Tom Rini364d0022023-01-10 11:19:45 -050013#ifndef CFG_SYS_CADMUS_BASE_REG
14#define CFG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
wdenk0aeb8532004-10-10 21:21:55 +000015#endif
16
17typedef struct cadmus_reg {
18 u_char cm_ver; /* Board version */
19 u_char cm_csr; /* General control/status */
20 u_char cm_rst; /* Reset control */
21 u_char cm_hsclk; /* High speed clock */
22 u_char cm_hsxclk; /* High speed clock extended */
23 u_char cm_led; /* LED data */
24 u_char cm_pci; /* PCI control/status */
25 u_char cm_dma; /* DMA control */
26 u_char cm_reserved[248]; /* Total 256 bytes */
27} cadmus_reg_t;
28
wdenk0aeb8532004-10-10 21:21:55 +000029unsigned int
30get_board_version(void)
31{
Tom Rini364d0022023-01-10 11:19:45 -050032 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
wdenk0aeb8532004-10-10 21:21:55 +000033
34 return cadmus->cm_ver;
35}
36
wdenk0aeb8532004-10-10 21:21:55 +000037unsigned long
Tom Riniaea2a992021-12-14 13:36:39 -050038get_board_sys_clk(void)
wdenk0aeb8532004-10-10 21:21:55 +000039{
Tom Rini364d0022023-01-10 11:19:45 -050040 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
wdenk0aeb8532004-10-10 21:21:55 +000041
42 uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
43
44 if (pci1_speed == 0) {
chenhui zhao701a8e42011-09-15 14:52:34 +080045 return 33333333;
wdenk0aeb8532004-10-10 21:21:55 +000046 } else if (pci1_speed == 1) {
chenhui zhao701a8e42011-09-15 14:52:34 +080047 return 66666666;
wdenk0aeb8532004-10-10 21:21:55 +000048 } else {
49 /* Really, unknown. Be safe? */
chenhui zhao701a8e42011-09-15 14:52:34 +080050 return 33333333;
wdenk0aeb8532004-10-10 21:21:55 +000051 }
52}
53
wdenk0aeb8532004-10-10 21:21:55 +000054unsigned int
55get_pci_slot(void)
56{
Tom Rini364d0022023-01-10 11:19:45 -050057 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
wdenk0aeb8532004-10-10 21:21:55 +000058
59 /*
60 * PCI slot in USER bits CSR[6:7] by convention.
61 */
62 return ((cadmus->cm_csr >> 6) & 0x3) + 1;
63}
64
wdenk0aeb8532004-10-10 21:21:55 +000065unsigned int
66get_pci_dual(void)
67{
Tom Rini364d0022023-01-10 11:19:45 -050068 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
wdenk0aeb8532004-10-10 21:21:55 +000069
70 /*
71 * PCI DUAL in CM_PCI[3]
72 */
73 return cadmus->cm_pci & 0x10;
74}