blob: e119330bc0c14a95c53e88f820765da001e5481a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Fabio Estevam1d97a592015-04-20 14:48:57 -03002/*
Josua Mayer101237a2022-05-19 12:31:59 +03003 * Copyright (C) 2022 Josua Mayer <josua@solid-run.com>
4 *
Fabio Estevam1d97a592015-04-20 14:48:57 -03005 * Copyright (C) 2015 Freescale Semiconductor, Inc.
6 *
7 * Author: Fabio Estevam <fabio.estevam@freescale.com>
8 *
9 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
10 *
11 * Based on SPL code from Solidrun tree, which is:
12 * Author: Tungyi Lin <tungyilin1127@gmail.com>
13 *
14 * Derived from EDM_CF_IMX6 code by TechNexion,Inc
15 * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
Fabio Estevam1d97a592015-04-20 14:48:57 -030016 */
17
Simon Glass1e268642020-05-10 11:39:55 -060018#include <common.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060019#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -070020#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060021#include <log.h>
Fabio Estevam1d97a592015-04-20 14:48:57 -030022#include <asm/arch/clock.h>
23#include <asm/arch/imx-regs.h>
24#include <asm/arch/iomux.h>
25#include <asm/arch/mx6-pins.h>
Fabio Estevam239fd312015-04-29 22:28:09 -030026#include <asm/arch/mxc_hdmi.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060027#include <env.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060028#include <asm/global_data.h>
Simon Glassdbd79542020-05-10 11:40:11 -060029#include <linux/delay.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090030#include <linux/errno.h>
Fabio Estevam1d97a592015-04-20 14:48:57 -030031#include <asm/gpio.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020032#include <asm/mach-imx/iomux-v3.h>
33#include <asm/mach-imx/sata.h>
34#include <asm/mach-imx/video.h>
Shiji Yangbb112342023-08-03 09:47:16 +080035#include <asm/sections.h>
Fabio Estevam1d97a592015-04-20 14:48:57 -030036#include <mmc.h>
Yangbo Lu73340382019-06-21 11:42:28 +080037#include <fsl_esdhc_imx.h>
Fabio Estevam444f0012015-05-04 11:22:55 -030038#include <malloc.h>
Fabio Estevam1d97a592015-04-20 14:48:57 -030039#include <asm/arch/crm_regs.h>
40#include <asm/io.h>
41#include <asm/arch/sys_proto.h>
Fabio Estevam1d97a592015-04-20 14:48:57 -030042#include <spl.h>
Fabio Estevam729bbb82015-04-29 22:28:10 -030043#include <usb.h>
Mateusz Kulikowski3add69e2016-03-31 23:12:23 +020044#include <usb/ehci-ci.h>
Josua Mayer101237a2022-05-19 12:31:59 +030045#include <netdev.h>
46#include <phy.h>
Fabio Estevam1d97a592015-04-20 14:48:57 -030047
48DECLARE_GLOBAL_DATA_PTR;
49
50#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
52 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
53
54#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
55 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
56 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
57
Fabio Estevam729bbb82015-04-29 22:28:10 -030058#define USB_H1_VBUS IMX_GPIO_NR(1, 0)
Fabio Estevam1d97a592015-04-20 14:48:57 -030059
Jon Nettleton30cba092018-06-07 16:17:36 +030060enum board_type {
61 CUBOXI = 0x00,
62 HUMMINGBOARD = 0x01,
63 HUMMINGBOARD2 = 0x02,
64 UNKNOWN = 0x03,
65};
66
Baruch Siach6d3f68c2019-11-10 14:38:07 +020067static struct gpio_desc board_detect_desc[5];
68
Jon Nettletondfe7fab2018-06-07 16:17:37 +030069#define MEM_STRIDE 0x4000000
70static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
71{
72 volatile u32 *addr;
73 u32 save[64];
74 u32 cnt;
75 u32 size;
76 int i = 0;
77
78 /* First save the data */
79 for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
80 addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */
81 sync ();
82 save[i++] = *addr;
83 sync ();
84 }
85
86 /* First write a signature */
87 * (volatile u32 *)base = 0x12345678;
88 for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
89 * (volatile u32 *)((u32)base + size) = size;
90 sync ();
91 if (* (volatile u32 *)((u32)base) == size) { /* We reached the overlapping address */
92 break;
93 }
94 }
95
96 /* Restore the data */
97 for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
98 addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */
99 sync ();
100 *addr = save[i--];
101 sync ();
102 }
103
104 return (size);
105}
106
Fabio Estevam1d97a592015-04-20 14:48:57 -0300107int dram_init(void)
108{
Jon Nettletondfe7fab2018-06-07 16:17:37 +0300109 u32 max_size = imx_ddr_size();
110
Tom Rinibb4dd962022-11-16 13:10:37 -0500111 gd->ram_size = get_ram_size_stride_test((u32 *) CFG_SYS_SDRAM_BASE,
Jon Nettletondfe7fab2018-06-07 16:17:37 +0300112 (u32)max_size);
113
Fabio Estevam1d97a592015-04-20 14:48:57 -0300114 return 0;
115}
116
117static iomux_v3_cfg_t const uart1_pads[] = {
Fabio Estevam5f402c42015-04-25 18:47:17 -0300118 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
119 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
Fabio Estevam1d97a592015-04-20 14:48:57 -0300120};
121
122static iomux_v3_cfg_t const usdhc2_pads[] = {
Fabio Estevam5f402c42015-04-25 18:47:17 -0300123 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
124 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
125 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
126 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
127 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
128 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
Fabio Estevam1d97a592015-04-20 14:48:57 -0300129};
130
Jon Nettleton08d38cb2018-06-11 15:26:20 +0300131static iomux_v3_cfg_t const usdhc3_pads[] = {
132 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
133 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
134 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
135 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
136 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
137 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
138 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
139 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
140 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
141 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
142 IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
143};
144
Jon Nettleton30cba092018-06-07 16:17:36 +0300145static iomux_v3_cfg_t const board_detect[] = {
Fabio Estevam7a2f9cd2015-04-25 18:47:19 -0300146 /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
147 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)),
148 IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
Jon Nettleton30cba092018-06-07 16:17:36 +0300149 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(UART_PAD_CTRL)),
150};
151
152static iomux_v3_cfg_t const som_rev_detect[] = {
153 /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
154 IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00 | MUX_PAD_CTRL(UART_PAD_CTRL)),
155 IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
Fabio Estevam7a2f9cd2015-04-25 18:47:19 -0300156};
157
Fabio Estevam1d97a592015-04-20 14:48:57 -0300158static void setup_iomux_uart(void)
159{
Fabio Estevam5f402c42015-04-25 18:47:17 -0300160 SETUP_IOMUX_PADS(uart1_pads);
Fabio Estevam1d97a592015-04-20 14:48:57 -0300161}
162
Jon Nettleton08d38cb2018-06-11 15:26:20 +0300163int board_mmc_get_env_dev(int devno)
164{
Baruch Siach6d3f68c2019-11-10 14:38:07 +0200165 return devno;
Jon Nettleton08d38cb2018-06-11 15:26:20 +0300166}
167
Fabio Estevam239fd312015-04-29 22:28:09 -0300168#ifdef CONFIG_VIDEO_IPUV3
169static void do_enable_hdmi(struct display_info_t const *dev)
170{
171 imx_enable_hdmi_phy();
172}
173
174struct display_info_t const displays[] = {
175 {
176 .bus = -1,
177 .addr = 0,
178 .pixfmt = IPU_PIX_FMT_RGB24,
179 .detect = detect_hdmi,
180 .enable = do_enable_hdmi,
181 .mode = {
182 .name = "HDMI",
183 /* 1024x768@60Hz (VESA)*/
184 .refresh = 60,
185 .xres = 1024,
186 .yres = 768,
187 .pixclock = 15384,
188 .left_margin = 160,
189 .right_margin = 24,
190 .upper_margin = 29,
191 .lower_margin = 3,
192 .hsync_len = 136,
193 .vsync_len = 6,
194 .sync = FB_SYNC_EXT,
195 .vmode = FB_VMODE_NONINTERLACED
196 }
197 }
198};
199
200size_t display_count = ARRAY_SIZE(displays);
201
202static int setup_display(void)
203{
204 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
205 int reg;
206 int timeout = 100000;
207
208 enable_ipu_clock();
209 imx_setup_hdmi();
210
211 /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
212 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
213
214 reg = readl(&ccm->analog_pll_video);
215 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
216 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
217 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
218 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
219 writel(reg, &ccm->analog_pll_video);
220
221 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
222 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
223
224 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
225 writel(reg, &ccm->analog_pll_video);
226
227 while (timeout--)
228 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
229 break;
230 if (timeout < 0) {
231 printf("Warning: video pll lock timeout!\n");
232 return -ETIMEDOUT;
233 }
234
235 reg = readl(&ccm->analog_pll_video);
236 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
237 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
238 writel(reg, &ccm->analog_pll_video);
239
240 /* gate ipu1_di0_clk */
241 clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
242
243 /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
244 reg = readl(&ccm->chsccdr);
245 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
246 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
247 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
248 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
249 (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
250 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
251 writel(reg, &ccm->chsccdr);
252
253 /* enable ipu1_di0_clk */
254 setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
255
256 return 0;
257}
258#endif /* CONFIG_VIDEO_IPUV3 */
259
Fabio Estevam4bc9de52020-06-18 20:21:20 -0300260static int setup_fec(void)
261{
262 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
263 int ret;
264
265 ret = enable_fec_anatop_clock(0, ENET_25MHZ);
266 if (ret)
267 return ret;
268
269 /* set gpr1[ENET_CLK_SEL] */
270 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
271
272 return 0;
273}
274
Fabio Estevam1d97a592015-04-20 14:48:57 -0300275int board_early_init_f(void)
276{
277 setup_iomux_uart();
Fabio Estevam239fd312015-04-29 22:28:09 -0300278
Troy Kiskyd64485e2023-03-13 14:31:40 -0700279 if (CONFIG_IS_ENABLED(SATA))
280 setup_sata();
Fabio Estevam4bc9de52020-06-18 20:21:20 -0300281 setup_fec();
282
Fabio Estevamf82f20c2017-09-22 23:45:31 -0300283 return 0;
Fabio Estevam1d97a592015-04-20 14:48:57 -0300284}
285
286int board_init(void)
287{
Fabio Estevamf82f20c2017-09-22 23:45:31 -0300288 int ret = 0;
289
Fabio Estevam1d97a592015-04-20 14:48:57 -0300290 /* address of boot parameters */
Tom Rinibb4dd962022-11-16 13:10:37 -0500291 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
Fabio Estevam1d97a592015-04-20 14:48:57 -0300292
Fabio Estevamf82f20c2017-09-22 23:45:31 -0300293#ifdef CONFIG_VIDEO_IPUV3
294 ret = setup_display();
295#endif
296
297 return ret;
Fabio Estevam1d97a592015-04-20 14:48:57 -0300298}
299
Baruch Siach6d3f68c2019-11-10 14:38:07 +0200300static int request_detect_gpios(void)
301{
302 int node;
303 int ret;
304
305 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
306 "solidrun,hummingboard-detect");
307 if (node < 0)
308 return -ENODEV;
309
310 ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
311 "detect-gpios", board_detect_desc,
312 ARRAY_SIZE(board_detect_desc), GPIOD_IS_IN);
313
314 return ret;
315}
316
317static int free_detect_gpios(void)
318{
319 return gpio_free_list_nodev(board_detect_desc,
320 ARRAY_SIZE(board_detect_desc));
321}
322
Jon Nettleton30cba092018-06-07 16:17:36 +0300323static enum board_type board_type(void)
Fabio Estevam7a2f9cd2015-04-25 18:47:19 -0300324{
Jon Nettleton30cba092018-06-07 16:17:36 +0300325 int val1, val2, val3;
Fabio Estevam7a2f9cd2015-04-25 18:47:19 -0300326
Jon Nettleton30cba092018-06-07 16:17:36 +0300327 SETUP_IOMUX_PADS(board_detect);
Fabio Estevam7a2f9cd2015-04-25 18:47:19 -0300328
329 /*
330 * Machine selection -
Jon Nettleton30cba092018-06-07 16:17:36 +0300331 * Machine val1, val2, val3
332 * ----------------------------
333 * HB2 x x 0
334 * HB rev 3.x x 0 x
335 * CBi 0 1 x
336 * HB 1 1 x
Fabio Estevam7a2f9cd2015-04-25 18:47:19 -0300337 */
338
Jon Nettleton30cba092018-06-07 16:17:36 +0300339 gpio_direction_input(IMX_GPIO_NR(2, 8));
340 val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
Fabio Estevam7a2f9cd2015-04-25 18:47:19 -0300341
Jon Nettleton30cba092018-06-07 16:17:36 +0300342 if (val3 == 0)
343 return HUMMINGBOARD2;
Dennis Gilmore52e61ba2017-08-24 10:49:43 -0500344
Jon Nettleton30cba092018-06-07 16:17:36 +0300345 gpio_direction_input(IMX_GPIO_NR(3, 4));
346 val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
Dennis Gilmore52e61ba2017-08-24 10:49:43 -0500347
Jon Nettleton30cba092018-06-07 16:17:36 +0300348 if (val2 == 0)
349 return HUMMINGBOARD;
Dennis Gilmore52e61ba2017-08-24 10:49:43 -0500350
Jon Nettleton30cba092018-06-07 16:17:36 +0300351 gpio_direction_input(IMX_GPIO_NR(4, 9));
352 val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
Dennis Gilmore52e61ba2017-08-24 10:49:43 -0500353
Jon Nettleton30cba092018-06-07 16:17:36 +0300354 if (val1 == 0) {
355 return CUBOXI;
356 } else {
357 return HUMMINGBOARD;
358 }
359}
360
361static bool is_rev_15_som(void)
362{
363 int val1, val2;
364 SETUP_IOMUX_PADS(som_rev_detect);
Dennis Gilmore52e61ba2017-08-24 10:49:43 -0500365
Jon Nettleton30cba092018-06-07 16:17:36 +0300366 val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
367 val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
368
369 if (val1 == 1 && val2 == 0)
Dennis Gilmore52e61ba2017-08-24 10:49:43 -0500370 return true;
Jon Nettleton30cba092018-06-07 16:17:36 +0300371
372 return false;
Dennis Gilmore52e61ba2017-08-24 10:49:43 -0500373}
374
Jon Nettleton51182112018-06-11 15:26:22 +0300375static bool has_emmc(void)
376{
377 struct mmc *mmc;
Baruch Siach6d3f68c2019-11-10 14:38:07 +0200378 mmc = find_mmc_device(2);
Jon Nettleton51182112018-06-11 15:26:22 +0300379 if (!mmc)
380 return 0;
Pali Rohár7c639622021-07-14 16:37:29 +0200381 return (mmc_get_op_cond(mmc, true) < 0) ? 0 : 1;
Jon Nettleton51182112018-06-11 15:26:22 +0300382}
383
Fabio Estevam1d97a592015-04-20 14:48:57 -0300384int checkboard(void)
385{
Baruch Siach6d3f68c2019-11-10 14:38:07 +0200386 request_detect_gpios();
387
Jon Nettleton30cba092018-06-07 16:17:36 +0300388 switch (board_type()) {
389 case CUBOXI:
390 puts("Board: MX6 Cubox-i");
391 break;
392 case HUMMINGBOARD:
393 puts("Board: MX6 HummingBoard");
394 break;
395 case HUMMINGBOARD2:
396 puts("Board: MX6 HummingBoard2");
397 break;
398 case UNKNOWN:
399 default:
400 puts("Board: Unknown\n");
401 goto out;
402 }
403
404 if (is_rev_15_som())
405 puts(" (som rev 1.5)\n");
Fabio Estevam7a2f9cd2015-04-25 18:47:19 -0300406 else
Jon Nettleton30cba092018-06-07 16:17:36 +0300407 puts("\n");
Fabio Estevam7a2f9cd2015-04-25 18:47:19 -0300408
Baruch Siach6d3f68c2019-11-10 14:38:07 +0200409 free_detect_gpios();
Jon Nettleton30cba092018-06-07 16:17:36 +0300410out:
Fabio Estevam1d97a592015-04-20 14:48:57 -0300411 return 0;
412}
413
Josua Mayer101237a2022-05-19 12:31:59 +0300414static int find_ethernet_phy(void)
415{
416 struct mii_dev *bus = NULL;
417 struct phy_device *phydev = NULL;
418 int phy_addr = -ENOENT;
419
420#ifdef CONFIG_FEC_MXC
421 bus = fec_get_miibus(ENET_BASE_ADDR, -1);
422 if (!bus)
423 return -ENOENT;
424
425 // scan address 0, 1, 4
426 phydev = phy_find_by_mask(bus, 0b00010011);
427 if (!phydev) {
428 free(bus);
429 return -ENOENT;
430 }
431 pr_debug("%s: detected ethernet phy at address %d\n", __func__, phydev->addr);
432 phy_addr = phydev->addr;
433
434 free(phydev);
435#endif
436
437 return phy_addr;
438}
439
440#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
441/*
442 * Configure the correct ethernet PHYs nodes in device-tree:
443 * - AR8035 at addresses 0 or 4: Cubox
444 * - AR8035 at address 0: HummingBoard, HummingBoard 2
445 * - ADIN1300 at address 1: since SoM rev 1.9
446 */
447int ft_board_setup(void *fdt, struct bd_info *bd)
448{
449 int node_phy0, node_phy1, node_phy4;
450 int ret, phy;
451 bool enable_phy0 = false, enable_phy1 = false, enable_phy4 = false;
Josua Mayer5674e4c2022-06-16 11:40:15 +0300452 enum board_type board;
453
454 // detect device
455 request_detect_gpios();
456 board = board_type();
457 free_detect_gpios();
Josua Mayer101237a2022-05-19 12:31:59 +0300458
459 // detect phy
460 phy = find_ethernet_phy();
461 if (phy == 0 || phy == 4) {
462 enable_phy0 = true;
Josua Mayer5674e4c2022-06-16 11:40:15 +0300463 switch (board) {
464 case HUMMINGBOARD:
465 case HUMMINGBOARD2:
466 /* atheros phy may appear only at address 0 */
467 break;
Josua Mayer101237a2022-05-19 12:31:59 +0300468 case CUBOXI:
469 case UNKNOWN:
470 default:
Josua Mayer5674e4c2022-06-16 11:40:15 +0300471 /* atheros phy may appear at either address 0 or 4 */
Josua Mayer101237a2022-05-19 12:31:59 +0300472 enable_phy4 = true;
473 }
474 } else if (phy == 1) {
475 enable_phy1 = true;
476 } else {
477 pr_err("%s: couldn't detect ethernet phy, not patching dtb!\n", __func__);
478 return 0;
479 }
480
481 // update all phy nodes status
482 node_phy0 = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@0");
483 ret = fdt_setprop_string(fdt, node_phy0, "status", enable_phy0 ? "okay" : "disabled");
484 if (ret < 0 && enable_phy0)
485 pr_err("%s: failed to enable ethernet phy at address 0 in dtb!\n", __func__);
486 node_phy1 = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@1");
487 ret = fdt_setprop_string(fdt, node_phy1, "status", enable_phy1 ? "okay" : "disabled");
488 if (ret < 0 && enable_phy1)
489 pr_err("%s: failed to enable ethernet phy at address 1 in dtb!\n", __func__);
490 node_phy4 = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@4");
491 ret = fdt_setprop_string(fdt, node_phy4, "status", enable_phy4 ? "okay" : "disabled");
492 if (ret < 0 && enable_phy4)
493 pr_err("%s: failed to enable ethernet phy at address 4 in dtb!\n", __func__);
494
495 return 0;
496}
497#endif
498
Baruch Siach6d3f68c2019-11-10 14:38:07 +0200499/* Override the default implementation, DT model is not accurate */
500int show_board_info(void)
501{
502 return checkboard();
503}
504
Fabio Estevam9887c1a2015-04-25 18:47:21 -0300505int board_late_init(void)
506{
507#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Baruch Siach6d3f68c2019-11-10 14:38:07 +0200508 request_detect_gpios();
509
Jon Nettleton30cba092018-06-07 16:17:36 +0300510 switch (board_type()) {
511 case CUBOXI:
512 env_set("board_name", "CUBOXI");
513 break;
514 case HUMMINGBOARD:
Simon Glass6a38e412017-08-03 12:22:09 -0600515 env_set("board_name", "HUMMINGBOARD");
Jon Nettleton30cba092018-06-07 16:17:36 +0300516 break;
517 case HUMMINGBOARD2:
518 env_set("board_name", "HUMMINGBOARD2");
519 break;
520 case UNKNOWN:
521 default:
Simon Glass6a38e412017-08-03 12:22:09 -0600522 env_set("board_name", "CUBOXI");
Jon Nettleton30cba092018-06-07 16:17:36 +0300523 }
Fabio Estevam9887c1a2015-04-25 18:47:21 -0300524
Breno Limaba776122016-07-22 09:11:30 -0300525 if (is_mx6dq())
Simon Glass6a38e412017-08-03 12:22:09 -0600526 env_set("board_rev", "MX6Q");
Fabio Estevam9887c1a2015-04-25 18:47:21 -0300527 else
Simon Glass6a38e412017-08-03 12:22:09 -0600528 env_set("board_rev", "MX6DL");
Jon Nettleton30cba092018-06-07 16:17:36 +0300529
530 if (is_rev_15_som())
531 env_set("som_rev", "V15");
Jon Nettleton51182112018-06-11 15:26:22 +0300532
533 if (has_emmc())
534 env_set("has_emmc", "yes");
535
Baruch Siach6d3f68c2019-11-10 14:38:07 +0200536 free_detect_gpios();
Fabio Estevam9887c1a2015-04-25 18:47:21 -0300537#endif
538
539 return 0;
540}
541
Baruch Siach6d3f68c2019-11-10 14:38:07 +0200542/*
543 * This is not a perfect match. Avoid dependency on the DM GPIO driver needed
544 * for accurate board detection. Hummingboard2 DT is good enough for U-Boot on
545 * all Hummingboard/Cubox-i platforms.
546 */
547int board_fit_config_name_match(const char *name)
548{
549 char tmp_name[36];
550
551 snprintf(tmp_name, sizeof(tmp_name), "%s-hummingboard2-emmc-som-v15",
552 is_mx6dq() ? "imx6q" : "imx6dl");
553
554 return strcmp(name, tmp_name);
555}
556
Walter Lozanof74f7e82020-05-19 15:24:22 -0300557void board_boot_order(u32 *spl_boot_list)
558{
559 struct src *psrc = (struct src *)SRC_BASE_ADDR;
560 unsigned int reg = readl(&psrc->sbmr1) >> 11;
561 u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
562 unsigned int bmode = readl(&src_base->sbmr2);
563
564 /* If bmode is serial or USB phy is active, return serial */
565 if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
566 spl_boot_list[0] = BOOT_DEVICE_BOARD;
567 return;
568 }
569
570 switch (boot_mode >> IMX6_BMODE_SHIFT) {
571 case IMX6_BMODE_SD:
572 case IMX6_BMODE_ESD:
573 case IMX6_BMODE_MMC:
574 case IMX6_BMODE_EMMC:
575 /*
576 * Upon reading BOOT_CFG register the following map is done:
577 * Bit 11 and 12 of BOOT_CFG register can determine the current
578 * mmc port
579 * 0x1 SD2
580 * 0x2 SD3
581 */
582
583 reg &= 0x3; /* Only care about bottom 2 bits */
584 switch (reg) {
585 case 1:
586 SETUP_IOMUX_PADS(usdhc2_pads);
587 spl_boot_list[0] = BOOT_DEVICE_MMC1;
588 break;
589 case 2:
590 SETUP_IOMUX_PADS(usdhc3_pads);
591 spl_boot_list[0] = BOOT_DEVICE_MMC2;
592 break;
593 }
594 break;
595 default:
596 /* By default use USB downloader */
597 spl_boot_list[0] = BOOT_DEVICE_BOARD;
598 break;
599 }
600
601 /* As a last resort, use serial downloader */
602 spl_boot_list[1] = BOOT_DEVICE_BOARD;
603}
604
Fabio Estevam1d97a592015-04-20 14:48:57 -0300605#ifdef CONFIG_SPL_BUILD
Fabio Estevam5f402c42015-04-25 18:47:17 -0300606#include <asm/arch/mx6-ddr.h>
Fabio Estevamcb601912015-04-25 18:47:18 -0300607static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
Fabio Estevam1d97a592015-04-20 14:48:57 -0300608 .dram_sdclk_0 = 0x00020030,
609 .dram_sdclk_1 = 0x00020030,
610 .dram_cas = 0x00020030,
611 .dram_ras = 0x00020030,
Jon Nettletoncd2020d2018-04-10 17:05:35 -0300612 .dram_reset = 0x000c0030,
Fabio Estevam1d97a592015-04-20 14:48:57 -0300613 .dram_sdcke0 = 0x00003000,
614 .dram_sdcke1 = 0x00003000,
615 .dram_sdba2 = 0x00000000,
616 .dram_sdodt0 = 0x00003030,
617 .dram_sdodt1 = 0x00003030,
618 .dram_sdqs0 = 0x00000030,
619 .dram_sdqs1 = 0x00000030,
620 .dram_sdqs2 = 0x00000030,
621 .dram_sdqs3 = 0x00000030,
622 .dram_sdqs4 = 0x00000030,
623 .dram_sdqs5 = 0x00000030,
624 .dram_sdqs6 = 0x00000030,
625 .dram_sdqs7 = 0x00000030,
626 .dram_dqm0 = 0x00020030,
627 .dram_dqm1 = 0x00020030,
628 .dram_dqm2 = 0x00020030,
629 .dram_dqm3 = 0x00020030,
630 .dram_dqm4 = 0x00020030,
631 .dram_dqm5 = 0x00020030,
632 .dram_dqm6 = 0x00020030,
633 .dram_dqm7 = 0x00020030,
634};
635
Fabio Estevamcb601912015-04-25 18:47:18 -0300636static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
637 .dram_sdclk_0 = 0x00000028,
638 .dram_sdclk_1 = 0x00000028,
639 .dram_cas = 0x00000028,
640 .dram_ras = 0x00000028,
641 .dram_reset = 0x000c0028,
642 .dram_sdcke0 = 0x00003000,
643 .dram_sdcke1 = 0x00003000,
644 .dram_sdba2 = 0x00000000,
645 .dram_sdodt0 = 0x00003030,
646 .dram_sdodt1 = 0x00003030,
647 .dram_sdqs0 = 0x00000028,
648 .dram_sdqs1 = 0x00000028,
649 .dram_sdqs2 = 0x00000028,
650 .dram_sdqs3 = 0x00000028,
651 .dram_sdqs4 = 0x00000028,
652 .dram_sdqs5 = 0x00000028,
653 .dram_sdqs6 = 0x00000028,
654 .dram_sdqs7 = 0x00000028,
655 .dram_dqm0 = 0x00000028,
656 .dram_dqm1 = 0x00000028,
657 .dram_dqm2 = 0x00000028,
658 .dram_dqm3 = 0x00000028,
659 .dram_dqm4 = 0x00000028,
660 .dram_dqm5 = 0x00000028,
661 .dram_dqm6 = 0x00000028,
662 .dram_dqm7 = 0x00000028,
663};
664
665static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
Fabio Estevam1d97a592015-04-20 14:48:57 -0300666 .grp_ddr_type = 0x000C0000,
667 .grp_ddrmode_ctl = 0x00020000,
668 .grp_ddrpke = 0x00000000,
669 .grp_addds = 0x00000030,
670 .grp_ctlds = 0x00000030,
671 .grp_ddrmode = 0x00020000,
672 .grp_b0ds = 0x00000030,
673 .grp_b1ds = 0x00000030,
674 .grp_b2ds = 0x00000030,
675 .grp_b3ds = 0x00000030,
676 .grp_b4ds = 0x00000030,
677 .grp_b5ds = 0x00000030,
678 .grp_b6ds = 0x00000030,
679 .grp_b7ds = 0x00000030,
680};
681
Fabio Estevamcb601912015-04-25 18:47:18 -0300682static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
683 .grp_ddr_type = 0x000c0000,
684 .grp_ddrmode_ctl = 0x00020000,
685 .grp_ddrpke = 0x00000000,
686 .grp_addds = 0x00000028,
687 .grp_ctlds = 0x00000028,
688 .grp_ddrmode = 0x00020000,
689 .grp_b0ds = 0x00000028,
690 .grp_b1ds = 0x00000028,
691 .grp_b2ds = 0x00000028,
692 .grp_b3ds = 0x00000028,
693 .grp_b4ds = 0x00000028,
694 .grp_b5ds = 0x00000028,
695 .grp_b6ds = 0x00000028,
696 .grp_b7ds = 0x00000028,
697};
698
699/* microSOM with Dual processor and 1GB memory */
700static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
701 .p0_mpwldectrl0 = 0x00000000,
702 .p0_mpwldectrl1 = 0x00000000,
703 .p1_mpwldectrl0 = 0x00000000,
704 .p1_mpwldectrl1 = 0x00000000,
705 .p0_mpdgctrl0 = 0x0314031c,
706 .p0_mpdgctrl1 = 0x023e0304,
707 .p1_mpdgctrl0 = 0x03240330,
708 .p1_mpdgctrl1 = 0x03180260,
709 .p0_mprddlctl = 0x3630323c,
710 .p1_mprddlctl = 0x3436283a,
711 .p0_mpwrdlctl = 0x36344038,
712 .p1_mpwrdlctl = 0x422a423c,
713};
714
715/* microSOM with Quad processor and 2GB memory */
716static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
Fabio Estevam1d97a592015-04-20 14:48:57 -0300717 .p0_mpwldectrl0 = 0x00000000,
718 .p0_mpwldectrl1 = 0x00000000,
719 .p1_mpwldectrl0 = 0x00000000,
720 .p1_mpwldectrl1 = 0x00000000,
721 .p0_mpdgctrl0 = 0x0314031c,
722 .p0_mpdgctrl1 = 0x023e0304,
723 .p1_mpdgctrl0 = 0x03240330,
724 .p1_mpdgctrl1 = 0x03180260,
725 .p0_mprddlctl = 0x3630323c,
726 .p1_mprddlctl = 0x3436283a,
727 .p0_mpwrdlctl = 0x36344038,
728 .p1_mpwrdlctl = 0x422a423c,
729};
730
Fabio Estevamcb601912015-04-25 18:47:18 -0300731/* microSOM with Solo processor and 512MB memory */
732static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
733 .p0_mpwldectrl0 = 0x0045004D,
734 .p0_mpwldectrl1 = 0x003A0047,
735 .p0_mpdgctrl0 = 0x023C0224,
736 .p0_mpdgctrl1 = 0x02000220,
737 .p0_mprddlctl = 0x44444846,
738 .p0_mpwrdlctl = 0x32343032,
739};
740
741/* microSOM with Dual lite processor and 1GB memory */
742static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
743 .p0_mpwldectrl0 = 0x0045004D,
744 .p0_mpwldectrl1 = 0x003A0047,
745 .p1_mpwldectrl0 = 0x001F001F,
746 .p1_mpwldectrl1 = 0x00210035,
747 .p0_mpdgctrl0 = 0x023C0224,
748 .p0_mpdgctrl1 = 0x02000220,
749 .p1_mpdgctrl0 = 0x02200220,
Fabio Estevam4461e1e2015-05-29 13:00:36 -0300750 .p1_mpdgctrl1 = 0x02040208,
Fabio Estevamcb601912015-04-25 18:47:18 -0300751 .p0_mprddlctl = 0x44444846,
752 .p1_mprddlctl = 0x4042463C,
753 .p0_mpwrdlctl = 0x32343032,
754 .p1_mpwrdlctl = 0x36363430,
755};
756
757static struct mx6_ddr3_cfg mem_ddr_2g = {
Fabio Estevam1d97a592015-04-20 14:48:57 -0300758 .mem_speed = 1600,
759 .density = 2,
760 .width = 16,
761 .banks = 8,
762 .rowaddr = 14,
763 .coladdr = 10,
764 .pagesz = 2,
765 .trcd = 1375,
766 .trcmin = 4875,
767 .trasmin = 3500,
Fabio Estevam1d97a592015-04-20 14:48:57 -0300768};
769
Fabio Estevamcb601912015-04-25 18:47:18 -0300770static struct mx6_ddr3_cfg mem_ddr_4g = {
771 .mem_speed = 1600,
772 .density = 4,
773 .width = 16,
774 .banks = 8,
Jon Nettletondfe7fab2018-06-07 16:17:37 +0300775 .rowaddr = 16,
Fabio Estevamcb601912015-04-25 18:47:18 -0300776 .coladdr = 10,
777 .pagesz = 2,
778 .trcd = 1375,
779 .trcmin = 4875,
780 .trasmin = 3500,
781};
782
Fabio Estevam1d97a592015-04-20 14:48:57 -0300783static void ccgr_init(void)
784{
785 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
786
787 writel(0x00C03F3F, &ccm->CCGR0);
788 writel(0x0030FC03, &ccm->CCGR1);
789 writel(0x0FFFC000, &ccm->CCGR2);
790 writel(0x3FF00000, &ccm->CCGR3);
791 writel(0x00FFF300, &ccm->CCGR4);
792 writel(0x0F0000C3, &ccm->CCGR5);
793 writel(0x000003FF, &ccm->CCGR6);
794}
795
Fabio Estevamcb601912015-04-25 18:47:18 -0300796static void spl_dram_init(int width)
Fabio Estevam1d97a592015-04-20 14:48:57 -0300797{
798 struct mx6_ddr_sysinfo sysinfo = {
799 /* width of data bus: 0=16, 1=32, 2=64 */
Fabio Estevamcb601912015-04-25 18:47:18 -0300800 .dsize = width / 32,
Fabio Estevam1d97a592015-04-20 14:48:57 -0300801 /* config for full 4GB range so that get_mem_size() works */
802 .cs_density = 32, /* 32Gb per CS */
803 .ncs = 1, /* single chip select */
804 .cs1_mirror = 0,
805 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
806 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
807 .walat = 1, /* Write additional latency */
808 .ralat = 5, /* Read additional latency */
809 .mif3_mode = 3, /* Command prediction working mode */
810 .bi_on = 1, /* Bank interleaving enabled */
811 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
812 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
Peng Fan77e86952015-08-17 16:11:03 +0800813 .ddr_type = DDR_TYPE_DDR3,
Fabio Estevamcb3c1212016-08-29 20:37:15 -0300814 .refsel = 1, /* Refresh cycles at 32KHz */
815 .refr = 7, /* 8 refresh commands per refresh cycle */
Fabio Estevam1d97a592015-04-20 14:48:57 -0300816 };
817
Breno Limaba776122016-07-22 09:11:30 -0300818 if (is_mx6dq())
Fabio Estevamcb601912015-04-25 18:47:18 -0300819 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
820 else
821 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
822
823 if (is_cpu_type(MXC_CPU_MX6D))
824 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
825 else if (is_cpu_type(MXC_CPU_MX6Q))
826 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
827 else if (is_cpu_type(MXC_CPU_MX6DL))
Fabio Estevam4461e1e2015-05-29 13:00:36 -0300828 mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
Fabio Estevamcb601912015-04-25 18:47:18 -0300829 else if (is_cpu_type(MXC_CPU_MX6SOLO))
830 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
Fabio Estevam1d97a592015-04-20 14:48:57 -0300831}
832
833void board_init_f(ulong dummy)
834{
835 /* setup AIPS and disable watchdog */
836 arch_cpu_init();
837
838 ccgr_init();
839 gpr_init();
840
841 /* iomux and setup of i2c */
842 board_early_init_f();
843
844 /* setup GP timer */
845 timer_init();
846
Baruch Siachad5944d2022-11-03 18:03:38 +0200847 /* Enable device tree and early DM support*/
848 spl_early_init();
849
Fabio Estevam1d97a592015-04-20 14:48:57 -0300850 /* UART clocks enabled and gd valid - init serial console */
851 preloader_console_init();
852
853 /* DDR initialization */
Fabio Estevamcb601912015-04-25 18:47:18 -0300854 if (is_cpu_type(MXC_CPU_MX6SOLO))
855 spl_dram_init(32);
856 else
857 spl_dram_init(64);
Fabio Estevam1d97a592015-04-20 14:48:57 -0300858
859 /* Clear the BSS. */
860 memset(__bss_start, 0, __bss_end - __bss_start);
861
862 /* load/boot image from boot device */
863 board_init_r(NULL, 0);
864}
865#endif