blob: f33194045f9eb015f1e3238935c90dc19a30e143 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Graeme Russa875dda2011-12-23 16:51:29 +11002/*
3 * (C) Copyright 2011
4 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russa875dda2011-12-23 16:51:29 +11005 */
Bin Meng535109a2015-08-13 00:29:10 -07006
Graeme Russa875dda2011-12-23 16:51:29 +11007#include <common.h>
Simon Glass6980b6b2019-11-14 12:57:45 -07008#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06009#include <asm/global_data.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090010#include <linux/errno.h>
Simon Glass004ba172015-01-01 16:18:11 -070011#include <asm/mtrr.h>
Graeme Russa875dda2011-12-23 16:51:29 +110012
13DECLARE_GLOBAL_DATA_PTR;
14
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110015int init_cache_f_r(void)
16{
Simon Glassa72a7ab2019-09-25 08:56:49 -060017 bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
18 IS_ENABLED(CONFIG_FSP_VERSION2);
Simon Glass004ba172015-01-01 16:18:11 -070019 int ret;
20
Simon Glass76f8bbe2021-06-27 17:51:03 -060021 /*
22 * Supported configurations:
23 *
24 * booting from slimbootloader - in that case the MTRRs are already set
25 * up
26 * booting with FSPv1 - MTRRs are already set up
27 * booting with FSPv2 - MTRRs must be set here
28 * booting from coreboot - in this case there is no SPL, so we set up
29 * the MTRRs here
30 * Note: if there is an SPL, then it has already set up MTRRs so we
31 * don't need to do that here
32 */
33 do_mtrr &= !IS_ENABLED(CONFIG_SPL) &&
34 !IS_ENABLED(CONFIG_FSP_VERSION1) &&
Simon Glassa72a7ab2019-09-25 08:56:49 -060035 !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
36
37 if (do_mtrr) {
38 ret = mtrr_commit(false);
39 /*
40 * If MTRR MSR is not implemented by the processor, just ignore
41 * it
42 */
43 if (ret && ret != -ENOSYS)
44 return ret;
45 }
46
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110047 /* Initialise the CPU cache(s) */
48 return init_cache();
49}