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git01.mediatek.com / filogic / uboot / 79efdf634f063cb5cb452d875c135fd3434afb6a / . / arch / arm / mach-imx / speed.c
blob: 0e81cc880a1a15b0415f0c7b9fc105a87983a36c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]2/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]8 */
9
10#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -0700[diff] [blame]11#include <clock_legacy.h>
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]12#include <asm/arch/imx-regs.h>
Stefano Babicac41d4d2010-03-05 17:54:37 +0100[diff] [blame]13#include <asm/arch/clock.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]14#include <asm/global_data.h>
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]15
Yangbo Lu73340382019-06-21 11:42:28 +0800[diff] [blame]16#ifdef CONFIG_FSL_ESDHC_IMX
John Rigby0d21ed02010-12-20 18:27:51 -0700[diff] [blame]17DECLARE_GLOBAL_DATA_PTR;
18#endif
19
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]20int get_clocks(void)
21{
Yangbo Lu73340382019-06-21 11:42:28 +0800[diff] [blame]22#ifdef CONFIG_FSL_ESDHC_IMX
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]23#ifdef CONFIG_FSL_USDHC
Tom Rini376b88a2022-10-28 20:27:13 -0400[diff] [blame]24#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]25 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
Tom Rini376b88a2022-10-28 20:27:13 -0400[diff] [blame]26#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]27 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Tom Rini376b88a2022-10-28 20:27:13 -0400[diff] [blame]28#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]29 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]30#else
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]31 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]32#endif
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]33#else
Tom Rini376b88a2022-10-28 20:27:13 -0400[diff] [blame]34#if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]35 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
Tom Rini376b88a2022-10-28 20:27:13 -0400[diff] [blame]36#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]37 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Tom Rini376b88a2022-10-28 20:27:13 -0400[diff] [blame]38#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]39 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]40#else
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]41 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]42#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]43#endif
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]44#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]45 return 0;
46}