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git01.mediatek.com / filogic / uboot / 79dd434b22e2dc01cd56d7a6f510b0ffaef6280f / . / drivers / gpio / bcm2835_gpio.c
blob: fbc641d662e4e481c99ab667107d623a71f78317 [file] [log] [blame]
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]1/*
2 * Copyright (C) 2012 Vikram Narayananan
3 * <vikram186@gmail.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]6 */
7
8#include <common.h>
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]9#include <dm.h>
10#include <errno.h>
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]11#include <asm/gpio.h>
12#include <asm/io.h>
13
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]14struct bcm2835_gpios {
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]15 struct bcm2835_gpio_regs *reg;
16};
17
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]18static int bcm2835_gpio_direction_input(struct udevice *dev, unsigned gpio)
19{
20 struct bcm2835_gpios *gpios = dev_get_priv(dev);
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]21 unsigned val;
22
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]23 val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]24 val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
25 val |= (BCM2835_GPIO_INPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]26 writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]27
28 return 0;
29}
30
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]31static int bcm2835_gpio_direction_output(struct udevice *dev, unsigned gpio,
32 int value)
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]33{
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]34 struct bcm2835_gpios *gpios = dev_get_priv(dev);
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]35 unsigned val;
36
37 gpio_set_value(gpio, value);
38
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]39 val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]40 val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
41 val |= (BCM2835_GPIO_OUTPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]42 writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]43
44 return 0;
45}
46
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]47static bool bcm2835_gpio_is_output(const struct bcm2835_gpios *gpios, int gpio)
48{
49 u32 val;
50
51 val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
52 val &= BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio);
53 return val ? true : false;
54}
55
56static int bcm2835_get_value(const struct bcm2835_gpios *gpios, unsigned gpio)
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]57{
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]58 unsigned val;
59
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]60 val = readl(&gpios->reg->gplev[BCM2835_GPIO_COMMON_BANK(gpio)]);
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]61
62 return (val >> BCM2835_GPIO_COMMON_SHIFT(gpio)) & 0x1;
63}
64
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]65static int bcm2835_gpio_get_value(struct udevice *dev, unsigned gpio)
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]66{
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]67 const struct bcm2835_gpios *gpios = dev_get_priv(dev);
68
69 return bcm2835_get_value(gpios, gpio);
70}
71
72static int bcm2835_gpio_set_value(struct udevice *dev, unsigned gpio,
73 int value)
74{
75 struct bcm2835_gpios *gpios = dev_get_priv(dev);
76 u32 *output_reg = value ? gpios->reg->gpset : gpios->reg->gpclr;
Stephen Warren45b8ae62012-08-05 16:07:21 +0000[diff] [blame]77
78 writel(1 << BCM2835_GPIO_COMMON_SHIFT(gpio),
79 &output_reg[BCM2835_GPIO_COMMON_BANK(gpio)]);
80
81 return 0;
82}
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]83
84static int bcm2835_gpio_get_function(struct udevice *dev, unsigned offset)
85{
86 struct bcm2835_gpios *gpios = dev_get_priv(dev);
87
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]88 /* GPIOF_FUNC is not implemented yet */
89 if (bcm2835_gpio_is_output(gpios, offset))
90 return GPIOF_OUTPUT;
91 else
92 return GPIOF_INPUT;
93}
94
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]95
96static const struct dm_gpio_ops gpio_bcm2835_ops = {
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]97 .direction_input = bcm2835_gpio_direction_input,
98 .direction_output = bcm2835_gpio_direction_output,
99 .get_value = bcm2835_gpio_get_value,
100 .set_value = bcm2835_gpio_set_value,
101 .get_function = bcm2835_gpio_get_function,
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]102};
103
104static int bcm2835_gpio_probe(struct udevice *dev)
105{
106 struct bcm2835_gpios *gpios = dev_get_priv(dev);
107 struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
Simon Glassde0977b2015-03-05 12:25:20 -0700[diff] [blame]108 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass74807622014-09-22 17:30:56 -0600[diff] [blame]109
110 uc_priv->bank_name = "GPIO";
111 uc_priv->gpio_count = BCM2835_GPIO_COUNT;
112 gpios->reg = (struct bcm2835_gpio_regs *)plat->base;
113
114 return 0;
115}
116
117U_BOOT_DRIVER(gpio_bcm2835) = {
118 .name = "gpio_bcm2835",
119 .id = UCLASS_GPIO,
120 .ops = &gpio_bcm2835_ops,
121 .probe = bcm2835_gpio_probe,
122 .priv_auto_alloc_size = sizeof(struct bcm2835_gpios),
123};