Linus Walleij | 7477139 | 2015-03-09 10:53:21 +0100 | [diff] [blame] | 1 | if ARM64 |
| 2 | |
Andre Przywara | 4eecab7 | 2018-07-25 00:57:01 +0100 | [diff] [blame] | 3 | config ARMV8_SPL_EXCEPTION_VECTORS |
| 4 | bool "Install crash dump exception vectors" |
| 5 | depends on SPL |
Alexander Graf | b3e9dc6 | 2019-02-20 17:14:49 +0100 | [diff] [blame] | 6 | default n |
Andre Przywara | 4eecab7 | 2018-07-25 00:57:01 +0100 | [diff] [blame] | 7 | help |
| 8 | The default exception vector table is only used for the crash |
| 9 | dump, but still takes quite a lot of space in the image size. |
| 10 | |
| 11 | Say N here if you are running out of code space in the image |
| 12 | and want to save some space at the cost of less debugging info. |
| 13 | |
Linus Walleij | 7477139 | 2015-03-09 10:53:21 +0100 | [diff] [blame] | 14 | config ARMV8_MULTIENTRY |
Masahiro Yamada | 78cd22a | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 15 | bool "Enable multiple CPUs to enter into U-Boot" |
Linus Walleij | 7477139 | 2015-03-09 10:53:21 +0100 | [diff] [blame] | 16 | |
Mingkai Hu | 553d405 | 2017-01-06 17:41:10 +0800 | [diff] [blame] | 17 | config ARMV8_SET_SMPEN |
| 18 | bool "Enable data coherency with other cores in cluster" |
| 19 | help |
| 20 | Say Y here if there is not any trust firmware to set |
| 21 | CPUECTLR_EL1.SMPEN bit before U-Boot. |
| 22 | |
| 23 | For A53, it enables data coherency with other cores in the |
| 24 | cluster, and for A57/A72, it enables receiving of instruction |
| 25 | cache and TLB maintenance operations. |
| 26 | Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even |
| 27 | for single core systems. Unfortunately write access to this |
| 28 | register may be controlled by EL3/EL2 firmware. To be more |
| 29 | precise, by default (if there is EL2/EL3 firmware running) |
| 30 | this register is RO for NS EL1. |
| 31 | This switch can be used to avoid writing to CPUECTLR_EL1, |
| 32 | it can be safely enabled when EL2/EL3 initialized SMPEN bit |
| 33 | or when CPU implementation doesn't include that register. |
| 34 | |
Masahiro Yamada | 2663cd6 | 2016-06-27 19:31:05 +0900 | [diff] [blame] | 35 | config ARMV8_SPIN_TABLE |
| 36 | bool "Support spin-table enable method" |
| 37 | depends on ARMV8_MULTIENTRY && OF_LIBFDT |
| 38 | help |
| 39 | Say Y here to support "spin-table" enable method for booting Linux. |
| 40 | |
| 41 | To use this feature, you must do: |
| 42 | - Specify enable-method = "spin-table" in each CPU node in the |
| 43 | Device Tree you are using to boot the kernel |
Masahiro Yamada | 04379f0 | 2017-01-20 18:04:43 +0900 | [diff] [blame] | 44 | - Bring secondary CPUs into U-Boot proper in a board specific |
| 45 | manner. This must be done *after* relocation. Otherwise, the |
| 46 | secondary CPUs will spin in unprotected memory area because the |
| 47 | master CPU protects the relocated spin code. |
Masahiro Yamada | 2663cd6 | 2016-06-27 19:31:05 +0900 | [diff] [blame] | 48 | |
| 49 | U-Boot automatically does: |
| 50 | - Set "cpu-release-addr" property of each CPU node |
| 51 | (overwrites it if already exists). |
| 52 | - Reserve the code for the spin-table and the release address |
| 53 | via a /memreserve/ region in the Device Tree. |
| 54 | |
Hou Zhiqiang | 2498c23 | 2017-01-16 17:31:47 +0800 | [diff] [blame] | 55 | menu "ARMv8 secure monitor firmware" |
| 56 | config ARMV8_SEC_FIRMWARE_SUPPORT |
| 57 | bool "Enable ARMv8 secure monitor firmware framework support" |
Hou Zhiqiang | 2498c23 | 2017-01-16 17:31:47 +0800 | [diff] [blame] | 58 | select FIT |
Michal Simek | 7e7ba3b | 2018-07-23 15:55:15 +0200 | [diff] [blame] | 59 | select OF_LIBFDT |
Hou Zhiqiang | 2498c23 | 2017-01-16 17:31:47 +0800 | [diff] [blame] | 60 | help |
| 61 | This framework is aimed at making secure monitor firmware load |
| 62 | process brief. |
| 63 | Note: Only FIT format image is supported. |
| 64 | You should prepare and provide the below information: |
| 65 | - Address of secure firmware. |
| 66 | - Address to hold the return address from secure firmware. |
| 67 | - Secure firmware FIT image related information. |
Thomas Hebb | 1dbd3d1 | 2019-11-10 08:23:15 -0800 | [diff] [blame] | 68 | Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME |
Hou Zhiqiang | 2498c23 | 2017-01-16 17:31:47 +0800 | [diff] [blame] | 69 | - The target exception level that secure monitor firmware will |
| 70 | return to. |
| 71 | |
| 72 | config SPL_ARMV8_SEC_FIRMWARE_SUPPORT |
| 73 | bool "Enable ARMv8 secure monitor firmware framework support for SPL" |
Hou Zhiqiang | 2498c23 | 2017-01-16 17:31:47 +0800 | [diff] [blame] | 74 | select SPL_FIT |
Michal Simek | 7e7ba3b | 2018-07-23 15:55:15 +0200 | [diff] [blame] | 75 | select SPL_OF_LIBFDT |
Hou Zhiqiang | 2498c23 | 2017-01-16 17:31:47 +0800 | [diff] [blame] | 76 | help |
| 77 | Say Y here to support this framework in SPL phase. |
| 78 | |
Peng Fan | 617fc29 | 2020-05-05 20:28:41 +0800 | [diff] [blame] | 79 | config SPL_RECOVER_DATA_SECTION |
| 80 | bool "save/restore SPL data section" |
| 81 | help |
| 82 | Say Y here to save SPL data section for cold boot, and restore |
| 83 | at warm boot in SPL phase. |
| 84 | |
Hou Zhiqiang | 6be115d | 2017-01-16 17:31:48 +0800 | [diff] [blame] | 85 | config SEC_FIRMWARE_ARMV8_PSCI |
| 86 | bool "PSCI implementation in secure monitor firmware" |
| 87 | depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT |
| 88 | help |
| 89 | This config enables the ARMv8 PSCI implementation in secure monitor |
| 90 | firmware. This is a private PSCI implementation and different from |
| 91 | those implemented under the common ARMv8 PSCI framework. |
| 92 | |
Hou Zhiqiang | 2498c23 | 2017-01-16 17:31:47 +0800 | [diff] [blame] | 93 | config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT |
| 94 | bool "ARMv8 secure monitor firmware ERET address byteorder swap" |
| 95 | depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT |
| 96 | help |
| 97 | Say Y here when the endianness of the register or memory holding the |
| 98 | Secure firmware exception return address is different with core's. |
| 99 | |
| 100 | endmenu |
| 101 | |
Alexander Graf | 68a14f7 | 2016-08-16 21:08:48 +0200 | [diff] [blame] | 102 | config PSCI_RESET |
| 103 | bool "Use PSCI for reset and shutdown" |
| 104 | default y |
Heinrich Schuchardt | 26f09d0 | 2018-10-18 12:29:40 +0200 | [diff] [blame] | 105 | select ARM_SMCCC if OF_CONTROL |
Bhaskar Upadhaya | 4270381 | 2018-01-11 20:03:30 +0530 | [diff] [blame] | 106 | depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \ |
Tom Rini | 48425b1 | 2021-02-09 08:03:10 -0500 | [diff] [blame] | 107 | !TARGET_LS2080AQDS && \ |
Bhaskar Upadhaya | 4270381 | 2018-01-11 20:03:30 +0530 | [diff] [blame] | 108 | !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \ |
Ashish Kumar | 1ef4c77 | 2017-08-31 16:12:55 +0530 | [diff] [blame] | 109 | !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \ |
Alexander Graf | 68a14f7 | 2016-08-16 21:08:48 +0200 | [diff] [blame] | 110 | !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ |
Bhaskar Upadhaya | 7fff22a | 2018-01-11 20:03:31 +0530 | [diff] [blame] | 111 | !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \ |
Bhaskar Upadhaya | 5e6f598 | 2018-05-23 11:03:30 +0530 | [diff] [blame] | 112 | !TARGET_LS1012AFRWY && \ |
Yuantian Tang | 473bbc4 | 2019-04-10 16:43:35 +0800 | [diff] [blame] | 113 | !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \ |
Alexander Graf | 7a2aa8f | 2016-11-17 01:02:55 +0100 | [diff] [blame] | 114 | !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ |
| 115 | !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 116 | !TARGET_LS1046AFRWY && \ |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 117 | !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ |
Meenakshi Aggarwal | ccb5d5d | 2020-10-29 19:16:16 +0530 | [diff] [blame] | 118 | !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ |
Tom Rini | 79d9a96 | 2021-02-20 20:05:49 -0500 | [diff] [blame^] | 119 | !ARCH_UNIPHIER |
Alexander Graf | 68a14f7 | 2016-08-16 21:08:48 +0200 | [diff] [blame] | 120 | help |
| 121 | Most armv8 systems have PSCI support enabled in EL3, either through |
| 122 | ARM Trusted Firmware or other firmware. |
| 123 | |
| 124 | On these systems, we do not need to implement system reset manually, |
| 125 | but can instead rely on higher level firmware to deal with it. |
| 126 | |
| 127 | Select Y here to make use of PSCI calls for system reset |
| 128 | |
macro.wave.z@gmail.com | 01bd334 | 2016-12-08 11:58:22 +0800 | [diff] [blame] | 129 | config ARMV8_PSCI |
| 130 | bool "Enable PSCI support" if EXPERT |
| 131 | default n |
| 132 | help |
| 133 | PSCI is Power State Coordination Interface defined by ARM. |
| 134 | The PSCI in U-boot provides a general framework and each platform |
| 135 | can implement their own specific PSCI functions. |
| 136 | Say Y here to enable PSCI support on ARMv8 platform. |
| 137 | |
| 138 | config ARMV8_PSCI_NR_CPUS |
| 139 | int "Maximum supported CPUs for PSCI" |
| 140 | depends on ARMV8_PSCI |
| 141 | default 4 |
| 142 | help |
| 143 | The maximum number of CPUs supported in the PSCI firmware. |
| 144 | It is no problem to set a larger value than the number of CPUs in |
| 145 | the actual hardware implementation. |
| 146 | |
macro.wave.z@gmail.com | 6a66c9b | 2016-12-08 11:58:24 +0800 | [diff] [blame] | 147 | config ARMV8_PSCI_CPUS_PER_CLUSTER |
| 148 | int "Number of CPUs per cluster" |
| 149 | depends on ARMV8_PSCI |
| 150 | default 0 |
| 151 | help |
| 152 | The number of CPUs per cluster, suppose each cluster has same number |
| 153 | of CPU cores, platforms with asymmetric clusters don't apply here. |
| 154 | A value 0 or no definition of it works for single cluster system. |
| 155 | System with multi-cluster should difine their own exact value. |
| 156 | |
Chee Hong Ang | 132567e | 2018-08-20 10:57:35 -0700 | [diff] [blame] | 157 | config ARMV8_EA_EL3_FIRST |
| 158 | bool "External aborts and SError interrupt exception are taken in EL3" |
| 159 | default n |
| 160 | help |
| 161 | Exception handling at all exception levels for External Abort and |
| 162 | SError interrupt exception are taken in EL3. |
| 163 | |
macro.wave.z@gmail.com | 01bd334 | 2016-12-08 11:58:22 +0800 | [diff] [blame] | 164 | if SYS_HAS_ARMV8_SECURE_BASE |
| 165 | |
| 166 | config ARMV8_SECURE_BASE |
| 167 | hex "Secure address for PSCI image" |
| 168 | depends on ARMV8_PSCI |
| 169 | help |
| 170 | Address for placing the PSCI text, data and stack sections. |
| 171 | If not defined, the PSCI sections are placed together with the u-boot |
| 172 | but platform can choose to place PSCI code image separately in other |
| 173 | places such as some secure RAM built-in SOC etc. |
| 174 | |
| 175 | endif |
| 176 | |
Linus Walleij | 7477139 | 2015-03-09 10:53:21 +0100 | [diff] [blame] | 177 | endif |