blob: cd2272367b53a0df87e1cffee681270493dd353f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +01002/*
3 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
4 *
5 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6 * Copyright (C) 2007 Andrew Victor
Prasanthi Chellakumar0509c4e2018-10-09 11:46:40 -07007 * Copyright (C) 2018 Microchip Technology Inc.
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +01008 *
9 * Watchdog Timer (WDT) - System peripherals regsters.
10 * Based on AT91SAM9261 datasheet revision D.
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +010011 */
12
13#ifndef AT91_WDT_H
14#define AT91_WDT_H
15
Jens Scharsig698ad062010-02-03 22:46:01 +010016#ifdef __ASSEMBLY__
17
Eric Benard8e518ec2011-06-06 22:48:26 +000018#define AT91_ASM_WDT_MR (ATMEL_BASE_WDT + 0x04)
Jens Scharsig698ad062010-02-03 22:46:01 +010019
20#else
21
22typedef struct at91_wdt {
23 u32 cr;
24 u32 mr;
25 u32 sr;
26} at91_wdt_t;
27
28#endif
29
Prasanthi Chellakumar0509c4e2018-10-09 11:46:40 -070030/* Watchdog Control Register */
31#define AT91_WDT_CR 0x00
Jens Scharsig698ad062010-02-03 22:46:01 +010032#define AT91_WDT_CR_WDRSTT 1
33#define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */
34
Prasanthi Chellakumar0509c4e2018-10-09 11:46:40 -070035/* Watchdog Mode Register*/
36#define AT91_WDT_MR 0X04
Jens Scharsig698ad062010-02-03 22:46:01 +010037#define AT91_WDT_MR_WDV(x) (x & 0xfff)
38#define AT91_WDT_MR_WDFIEN 0x00001000
39#define AT91_WDT_MR_WDRSTEN 0x00002000
40#define AT91_WDT_MR_WDRPROC 0x00004000
41#define AT91_WDT_MR_WDDIS 0x00008000
42#define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16)
43#define AT91_WDT_MR_WDDBGHLT 0x10000000
44#define AT91_WDT_MR_WDIDLEHLT 0x20000000
45
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +010046#endif