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git01.mediatek.com / filogic / uboot / 7996857502f53f3435847620fdf08b8a7399f3ba / . / include / configs / db-88f6820-gp.h
blob: ac810b0cbc548bcd3932af3182b330a9ebabfd59 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]2/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]4 */
5
6#ifndef _CONFIG_DB_88F6820_GP_H
7#define _CONFIG_DB_88F6820_GP_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]12
Stefan Roese3dbf35c2015-08-06 14:27:36 +0200[diff] [blame]13/*
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
16 * U-Boot into it.
17 */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]18#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
19
20/*
21 * Commands configuration
22 */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]23
24/* I2C */
25#define CONFIG_SYS_I2C
26#define CONFIG_SYS_I2C_MVTWSI
27#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
28#define CONFIG_SYS_I2C_SLAVE 0x0
29#define CONFIG_SYS_I2C_SPEED 100000
30
31/* SPI NOR flash default params, used by sf commands */
32#define CONFIG_SF_DEFAULT_SPEED 1000000
33#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]34
Stefan Roese1746e872015-06-29 14:58:11 +0200[diff] [blame]35/*
36 * SDIO/MMC Card Configuration
37 */
Stefan Roese1746e872015-06-29 14:58:11 +0200[diff] [blame]38#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
39
Stefan Roese10aad202015-06-29 14:58:14 +0200[diff] [blame]40/*
41 * SATA/SCSI/AHCI configuration
42 */
Stefan Roese10aad202015-06-29 14:58:14 +0200[diff] [blame]43#define CONFIG_SCSI_AHCI_PLAT
44#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
45#define CONFIG_SYS_SCSI_MAX_LUN 1
46#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
47 CONFIG_SYS_SCSI_MAX_LUN)
48
Stefan Roese2feb2262015-06-29 14:58:16 +0200[diff] [blame]49/* USB/EHCI configuration */
Stefan Roese2feb2262015-06-29 14:58:16 +0200[diff] [blame]50#define CONFIG_EHCI_IS_TDI
51
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]52/* Environment in SPI NOR flash */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]53#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
54#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
55#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
56
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]57#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
58
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]59/* PCIe support */
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]60#ifndef CONFIG_SPL_BUILD
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]61#define CONFIG_PCI_MVEBU
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]62#define CONFIG_PCI_SCAN_SHOW
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]63#endif
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]64
Kevin Smith2366bcc2015-05-18 16:09:46 +0000[diff] [blame]65/* Keep device tree and initrd in lower memory so the kernel can access them */
66#define CONFIG_EXTRA_ENV_SETTINGS \
67 "fdt_high=0x10000000\0" \
68 "initrd_high=0x10000000\0"
69
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]70/* SPL */
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]71/*
72 * Select the boot device here
73 *
74 * Currently supported are:
75 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
76 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
77 */
78#define SPL_BOOT_SPI_NOR_FLASH 1
79#define SPL_BOOT_SDIO_MMC_CARD 2
80#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
81
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]82/* Defines for SPL */
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]83#define CONFIG_SPL_SIZE (140 << 10)
84#define CONFIG_SPL_TEXT_BASE 0x40000030
85#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
86
87#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
88#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
89
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]90#ifdef CONFIG_SPL_BUILD
91#define CONFIG_SYS_MALLOC_SIMPLE
92#endif
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]93
94#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
95#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
96
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]97#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]98/* SPL related SPI defines */
Stefan Roese49e7d772015-11-20 13:51:57 +0100[diff] [blame]99#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]100#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
101#endif
102
103#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
104/* SPL related MMC defines */
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]105#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
106#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]107#ifdef CONFIG_SPL_BUILD
108#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
109#endif
110#endif
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]111
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]112/*
113 * mv-common.h should be defined after CMD configs since it used them
114 * to enable certain macros
115 */
116#include "mv-common.h"
117
118#endif /* _CONFIG_DB_88F6820_GP_H */