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git01.mediatek.com / filogic / uboot / 7944833b6960666bb16f07c3a2682c7bcbee426c / . / arch / powerpc / cpu / mpc85xx / p5040_serdes.c
blob: 409f2ac938d1f1e50cf9bae791373ed0f693e5e6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]2/*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]4 */
5
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]6#include <asm/fsl_serdes.h>
7#include <asm/processor.h>
8#include <asm/io.h>
9#include "fsl_corenet_serdes.h"
10
11/*
12 * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame]13 * U-Boot only supports one SerDes controller. Therefore, we ignore bank 4 in
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]14 * this table. This works because most of the SerDes code is for errata
15 * work-arounds, and there are no P5040 errata that effect bank 4.
16 */
17
18static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
19 [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
20 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
21 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
22 XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
23 [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
24 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
25 XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
26 XAUI_FM2, /* SATA1, SATA2 */ },
27 [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
28 SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
29 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
30 XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
31 [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
32 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
33 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
34 SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
35 /* SATA1, SATA2 */ },
36 [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
37 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
38 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
39 SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
40 /* SATA1, SATA2 */ },
41 [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
42 SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
43 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
44 XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
45 [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
46 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
47 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
48 XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
49 [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
50 SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
51 XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
52 XAUI_FM2, /* SATA1, SATA2 */ },
53 [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
54 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
55 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
56 /* NONE, NONE */ },
57 [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
58 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
59 NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
60 [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
61 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
62 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
63 XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
64 [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
65 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
66 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
67 NONE, SATA1, SATA2, /* NONE, NONE */ },
68 [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
69 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
70 XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
71 /* NONE, NONE */ },
72 [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
73 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
74 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
75 NONE, SATA1, SATA2, /* NONE, NONE */ },
76};
77
78enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
79{
80 if (!serdes_lane_enabled(lane))
81 return NONE;
82
83 return serdes_cfg_tbl[cfg][lane];
84}
85
86int is_serdes_prtcl_valid(u32 prtcl)
87{
88 int i;
89
Axel Linab95b092013-05-26 15:00:30 +0800[diff] [blame]90 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]91 return 0;
92
93 for (i = 0; i < SRDS_MAX_LANES; i++) {
94 if (serdes_cfg_tbl[prtcl][i] != NONE)
95 return 1;
96 }
97
98 return 0;
99}