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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Feng Li39e112d2016-11-03 14:15:17 +08002/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Biwen Lid15aa9f2019-12-31 15:33:44 +08004 * Copyright 2019 NXP
Feng Li39e112d2016-11-03 14:15:17 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Feng Li39e112d2016-11-03 14:15:17 +080010#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
11#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
12
Feng Li39e112d2016-11-03 14:15:17 +080013/*
14 * DDR: 800 MHz ( 1600 MT/s data rate )
15 */
16
17#define DDR_SDRAM_CFG 0x470c0008
18#define DDR_CS0_BNDS 0x008000bf
19#define DDR_CS0_CONFIG 0x80014302
20#define DDR_TIMING_CFG_0 0x50550004
21#define DDR_TIMING_CFG_1 0xbcb38c56
22#define DDR_TIMING_CFG_2 0x0040d120
23#define DDR_TIMING_CFG_3 0x010e1000
24#define DDR_TIMING_CFG_4 0x00000001
25#define DDR_TIMING_CFG_5 0x03401400
26#define DDR_SDRAM_CFG_2 0x00401010
27#define DDR_SDRAM_MODE 0x00061c60
28#define DDR_SDRAM_MODE_2 0x00180000
29#define DDR_SDRAM_INTERVAL 0x18600618
30#define DDR_DDR_WRLVL_CNTL 0x8655f605
31#define DDR_DDR_WRLVL_CNTL_2 0x05060607
32#define DDR_DDR_WRLVL_CNTL_3 0x05050505
33#define DDR_DDR_CDR1 0x80040000
34#define DDR_DDR_CDR2 0x00000001
35#define DDR_SDRAM_CLK_CNTL 0x02000000
36#define DDR_DDR_ZQ_CNTL 0x89080600
37#define DDR_CS0_CONFIG_2 0
38#define DDR_SDRAM_CFG_MEM_EN 0x80000000
39#define SDRAM_CFG2_D_INIT 0x00000010
40#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
41#define SDRAM_CFG2_FRC_SR 0x80000000
42#define SDRAM_CFG_BI 0x00000001
43
Feng Li39e112d2016-11-03 14:15:17 +080044#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
45#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
46
Feng Li39e112d2016-11-03 14:15:17 +080047/*
48 * Serial Port
49 */
Feng Li39e112d2016-11-03 14:15:17 +080050#define CONFIG_SYS_NS16550_SERIAL
51#define CONFIG_SYS_NS16550_REG_SIZE 1
52#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Feng Li39e112d2016-11-03 14:15:17 +080053
54/*
55 * I2C
56 */
Biwen Lid15aa9f2019-12-31 15:33:44 +080057
Feng Li39e112d2016-11-03 14:15:17 +080058/*
59 * MMC
60 */
Feng Li39e112d2016-11-03 14:15:17 +080061
62/* SATA */
Feng Li39e112d2016-11-03 14:15:17 +080063#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
64#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
65#endif
66#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
67 PCI_DEVICE_ID_FREESCALE_AHCI}
68
Feng Li39e112d2016-11-03 14:15:17 +080069/* SPI */
Feng Li39e112d2016-11-03 14:15:17 +080070
Feng Li39e112d2016-11-03 14:15:17 +080071/*
72 * eTSEC
73 */
Feng Li39e112d2016-11-03 14:15:17 +080074
75#ifdef CONFIG_TSEC_ENET
Feng Li39e112d2016-11-03 14:15:17 +080076#define CONFIG_MII_DEFAULT_TSEC 1
77#define CONFIG_TSEC1 1
78#define CONFIG_TSEC1_NAME "eTSEC1"
79#define CONFIG_TSEC2 1
80#define CONFIG_TSEC2_NAME "eTSEC2"
81
82#define TSEC1_PHY_ADDR 1
83#define TSEC2_PHY_ADDR 3
84
85#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
86#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
87
88#define TSEC1_PHYIDX 0
89#define TSEC2_PHYIDX 0
Feng Li39e112d2016-11-03 14:15:17 +080090#endif
91
Feng Li39e112d2016-11-03 14:15:17 +080092#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
93
Feng Li39e112d2016-11-03 14:15:17 +080094#define CONFIG_PEN_ADDR_BIG_ENDIAN
Feng Li39e112d2016-11-03 14:15:17 +080095#define CONFIG_SMP_PEN_ADDR 0x01ee0200
Feng Li39e112d2016-11-03 14:15:17 +080096
97#define CONFIG_HWCONFIG
98#define HWCONFIG_BUFFER_SIZE 256
99
100#define CONFIG_FSL_DEVICE_DISABLE
101
102#define CONFIG_EXTRA_ENV_SETTINGS \
103 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
Alison Wang71477062020-02-03 15:25:19 +0800104"initrd_high=0xffffffff\0"
Feng Li39e112d2016-11-03 14:15:17 +0800105
106/*
107 * Miscellaneous configurable options
108 */
Alison Wang71477062020-02-03 15:25:19 +0800109#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
110
Feng Li39e112d2016-11-03 14:15:17 +0800111#define CONFIG_LS102XA_STREAM_ID
112
Feng Li39e112d2016-11-03 14:15:17 +0800113#include <asm/fsl_secure_boot.h>
114
115#endif