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git01.mediatek.com / filogic / uboot / 7935f03370325a9b98076bb968ef678fa91964be / . / board / amcc / sequoia / init.S
blob: f876639d353fdca8c36b6fc0d17c165749d29783 [file] [log] [blame]
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]1/*
Matthias Fuchs62357702008-01-16 10:33:46 +0100[diff] [blame]2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]6 */
7
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]8#include <asm-offsets.h>
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]9#include <ppc_asm.tmpl>
Peter Tyser133c0fe2010-04-12 22:28:07 -0500[diff] [blame]10#include <asm/mmu.h>
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]11#include <config.h>
12
Matthias Fuchs62357702008-01-16 10:33:46 +0100[diff] [blame]13/*
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]14 * TLB TABLE
15 *
16 * This table is used by the cpu boot code to setup the initial tlb
17 * entries. Rather than make broad assumptions in the cpu source tree,
18 * this table lets each board set things up however they like.
19 *
20 * Pointer to the table is returned in r1
Matthias Fuchs62357702008-01-16 10:33:46 +0100[diff] [blame]21 */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]22 .section .bootpg,"ax"
23 .globl tlbtab
24
25tlbtab:
26 tlbtab_start
27
Niklaus Giger82e9f432008-01-10 18:50:33 +0100[diff] [blame]28 /* vxWorks needs this as first entry for the Machine Check interrupt */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]29 tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]30
Stefan Roesec20ef322009-05-11 13:46:14 +0200[diff] [blame]31 /*
32 * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
33 * entry is already configured for SDRAM via the JTAG debugger and mustn't
34 * be re-initialized by this RAM-booting U-Boot version.
35 */
36#ifndef CONFIG_SYS_RAMBOOT
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]37 /* TLB-entry for DDR SDRAM (Up to 2GB) */
Stefan Roese686816072007-10-31 20:57:11 +0100[diff] [blame]38#ifdef CONFIG_4xx_DCACHE
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]39 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G)
Stefan Roese686816072007-10-31 20:57:11 +0100[diff] [blame]40#else
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]41 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
Stefan Roese686816072007-10-31 20:57:11 +0100[diff] [blame]42#endif
Stefan Roesec20ef322009-05-11 13:46:14 +0200[diff] [blame]43#endif /* CONFIG_SYS_RAMBOOT */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]44
Niklaus Giger82e9f432008-01-10 18:50:33 +0100[diff] [blame]45 /* TLB-entry for EBC */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]46 tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG )
Niklaus Giger82e9f432008-01-10 18:50:33 +0100[diff] [blame]47
48 /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
49 * speed up boot process. It is patched after relocation to enable SA_I
50 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]51 tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
Niklaus Giger82e9f432008-01-10 18:50:33 +0100[diff] [blame]52
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]53#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]54 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]55 tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]56#endif
57
58 /* TLB-entry for PCI Memory */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]59 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
60 tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
61 tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
62 tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]63
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]64 /* TLB-entry for NAND */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]65 tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]66
67 /* TLB-entry for Internal Registers & OCM */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]68 tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]69
70 /*TLB-entry PCI registers*/
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]71 tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]72
73 /* TLB-entry for peripherals */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]74 tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]75
Gary Jennejohn9a1263f2007-08-31 15:21:46 +0200[diff] [blame]76 /* TLB-entry PCI IO Space - from sr@denx.de */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]77 tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
Gary Jennejohn9a1263f2007-08-31 15:21:46 +0200[diff] [blame]78
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]79 tlbtab_end