blob: e32cddec5993beece655fa61256d2bee9a7b13db [file] [log] [blame]
Kumar Galae38209e2011-02-09 02:00:08 +00001/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Galae38209e2011-02-09 02:00:08 +00005 */
6
7/*
8 * P3041 DS board configuration file
9 *
10 */
Kumar Galad0af3b92011-08-31 09:50:13 -050011#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
12
Kumar Galad0af3b92011-08-31 09:50:13 -050013#define CONFIG_NAND_FSL_ELBC
Zang Roy-R619112ce421a2012-11-26 00:05:38 +000014#define CONFIG_FSL_SATA_V2
Kumar Galad0af3b92011-08-31 09:50:13 -050015#define CONFIG_PCIE3
Kumar Galae38209e2011-02-09 02:00:08 +000016#define CONFIG_PCIE4
Kumar Gala4eb3c372011-10-14 13:28:52 -050017#define CONFIG_SYS_DPAA_RMAN
Kumar Galae38209e2011-02-09 02:00:08 +000018
Timur Tabi830b76f2012-10-05 09:48:53 +000019#define CONFIG_SYS_SRIO
20#define CONFIG_SRIO1 /* SRIO port 1 */
21#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gang27afb9c2013-05-07 16:30:46 +080022#define CONFIG_SRIO_PCIE_BOOT_MASTER
Kumar Galae38209e2011-02-09 02:00:08 +000023#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
24
25#include "corenet_ds.h"