wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 ELTEC Elektronik AG |
| 3 | * Frank Gottschling <fgottschling@eltec.de> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * board/config.h - configuration options, board specific |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H |
| 30 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 31 | #undef DEBUG |
| 32 | #define GTREGREAD(x) 0xffffffff /* needed for debug */ |
| 33 | |
| 34 | /* |
| 35 | * High Level Configuration Options |
| 36 | * (easy to change) |
| 37 | */ |
| 38 | |
| 39 | /* these hardware addresses are pretty bogus, please change them to |
| 40 | suit your needs */ |
| 41 | |
| 42 | /* first ethernet */ |
| 43 | #define CONFIG_ETHADDR 00:00:5b:ee:de:ad |
| 44 | |
| 45 | #define CONFIG_IPADDR 192.168.0.105 |
| 46 | #define CONFIG_SERVERIP 192.168.0.100 |
| 47 | |
| 48 | #define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */ |
| 49 | |
| 50 | #define CONFIG_BAUDRATE 9600 /* console baudrate */ |
| 51 | |
| 52 | #undef CONFIG_WATCHDOG |
| 53 | |
| 54 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 55 | |
| 56 | #define CONFIG_ZERO_BOOTDELAY_CHECK |
| 57 | |
| 58 | #undef CONFIG_BOOTARGS |
| 59 | #define CONFIG_BOOTCOMMAND \ |
| 60 | "bootp 1000000; " \ |
| 61 | "setenv bootargs root=ramfs console=ttyS00,9600 " \ |
| 62 | "ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):" \ |
| 63 | "$(netmask):$(hostname):eth0:none; " \ |
| 64 | "bootm" |
| 65 | |
| 66 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
| 67 | #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ |
| 68 | |
| 69 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
| 70 | |
| 71 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 72 | CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\ |
| 73 | CFG_CMD_FDC | CFG_CMD_ELF) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 74 | |
| 75 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
| 76 | #include <cmd_confdefs.h> |
| 77 | |
| 78 | /* |
| 79 | * Miscellaneous configurable options |
| 80 | */ |
| 81 | #define CFG_LONGHELP /* undef to save memory */ |
| 82 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 83 | |
| 84 | /* |
| 85 | * choose between COM1 and COM2 as serial console |
| 86 | */ |
| 87 | #define CONFIG_CONS_INDEX 1 |
| 88 | |
| 89 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 90 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 91 | #else |
| 92 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 93 | #endif |
| 94 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 95 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 96 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 97 | |
| 98 | #define CFG_MEMTEST_START 0x00000000 /* memtest works on */ |
| 99 | #define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ |
| 100 | |
| 101 | #define CFG_LOAD_ADDR 0x1000000 /* default load address */ |
| 102 | |
| 103 | #define CFG_HZ 1000 /* dec. freq: 1 ms ticks */ |
| 104 | |
| 105 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
| 106 | |
| 107 | /* |
| 108 | * Low Level Configuration Settings |
| 109 | * (address mappings, register initial values, etc.) |
| 110 | * You should know what you are doing if you make changes here. |
| 111 | */ |
| 112 | #define CFG_BOARD_ASM_INIT |
| 113 | #define CONFIG_MISC_INIT_R |
| 114 | |
| 115 | /* |
| 116 | * Choose the address mapping scheme for the MPC106 mem controller. |
| 117 | * Default is mapping B (CHRP), set this define to choose mapping A (PReP). |
| 118 | */ |
| 119 | #define CFG_ADDRESS_MAP_A |
| 120 | #ifdef CFG_ADDRESS_MAP_A |
| 121 | |
| 122 | #define CFG_PCI_MEMORY_BUS 0x80000000 |
| 123 | #define CFG_PCI_MEMORY_PHYS 0x00000000 |
| 124 | #define CFG_PCI_MEMORY_SIZE 0x80000000 |
| 125 | |
| 126 | #define CFG_PCI_MEM_BUS 0x00000000 |
| 127 | #define CFG_PCI_MEM_PHYS 0xc0000000 |
| 128 | #define CFG_PCI_MEM_SIZE 0x3f000000 |
| 129 | |
| 130 | #define CFG_ISA_MEM_BUS 0 |
| 131 | #define CFG_ISA_MEM_PHYS 0 |
| 132 | #define CFG_ISA_MEM_SIZE 0 |
| 133 | |
| 134 | #define CFG_PCI_IO_BUS 0x1000 |
| 135 | #define CFG_PCI_IO_PHYS 0x81000000 |
| 136 | #define CFG_PCI_IO_SIZE 0x01000000-CFG_PCI_IO_BUS |
| 137 | |
| 138 | #define CFG_ISA_IO_BUS 0x00000000 |
| 139 | #define CFG_ISA_IO_PHYS 0x80000000 |
| 140 | #define CFG_ISA_IO_SIZE 0x00800000 |
| 141 | |
| 142 | #else |
| 143 | |
| 144 | #define CFG_PCI_MEMORY_BUS 0x00000000 |
| 145 | #define CFG_PCI_MEMORY_PHYS 0x00000000 |
| 146 | #define CFG_PCI_MEMORY_SIZE 0x40000000 |
| 147 | |
| 148 | #define CFG_PCI_MEM_BUS 0x80000000 |
| 149 | #define CFG_PCI_MEM_PHYS 0x80000000 |
| 150 | #define CFG_PCI_MEM_SIZE 0x7d000000 |
| 151 | |
| 152 | #define CFG_ISA_MEM_BUS 0x00000000 |
| 153 | #define CFG_ISA_MEM_PHYS 0xfd000000 |
| 154 | #define CFG_ISA_MEM_SIZE 0x01000000 |
| 155 | |
| 156 | #define CFG_PCI_IO_BUS 0x00800000 |
| 157 | #define CFG_PCI_IO_PHYS 0xfe800000 |
| 158 | #define CFG_PCI_IO_SIZE 0x00400000 |
| 159 | |
| 160 | #define CFG_ISA_IO_BUS 0x00000000 |
| 161 | #define CFG_ISA_IO_PHYS 0xfe000000 |
| 162 | #define CFG_ISA_IO_SIZE 0x00800000 |
| 163 | |
| 164 | #endif /*CFG_ADDRESS_MAP_A */ |
| 165 | |
| 166 | #define CFG_60X_PCI_MEM_OFFSET 0x00000000 |
| 167 | |
| 168 | /* driver defines FDC,IDE,... */ |
| 169 | #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS |
| 170 | #define CFG_ISA_IO CFG_ISA_IO_PHYS |
| 171 | #define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS |
| 172 | |
| 173 | /* |
| 174 | * Start addresses for the final memory configuration |
| 175 | * (Set up by the startup code) |
| 176 | * Please note that CFG_SDRAM_BASE _must_ start at 0 |
| 177 | */ |
| 178 | #define CFG_SDRAM_BASE 0x00000000 |
| 179 | #define CFG_FLASH_BASE 0xfff00000 |
| 180 | |
| 181 | /* |
| 182 | * Definitions for initial stack pointer and data area |
| 183 | */ |
| 184 | #define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ |
| 185 | #define CFG_INIT_RAM_END 0x4000 |
| 186 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */ |
| 187 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 188 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 189 | |
| 190 | /* |
| 191 | * Flash mapping/organization on the MPC10x. |
| 192 | */ |
| 193 | #define FLASH_BASE0_PRELIM 0xff800000 |
| 194 | #define FLASH_BASE1_PRELIM 0xffc00000 |
| 195 | |
| 196 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 197 | #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
| 198 | |
| 199 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 200 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
| 201 | |
Wolfgang Denk | 47f5779 | 2005-08-08 01:03:24 +0200 | [diff] [blame] | 202 | /* |
| 203 | * JFFS2 partitions |
| 204 | * |
| 205 | */ |
| 206 | /* No command line, one static partition */ |
| 207 | #undef CONFIG_JFFS2_CMDLINE |
| 208 | #define CONFIG_JFFS2_DEV "nor" |
| 209 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF |
| 210 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 |
| 211 | |
| 212 | /* mtdparts command line support |
| 213 | * |
| 214 | * Note: fake mtd_id used, no linux mtd map file |
| 215 | */ |
| 216 | /* |
| 217 | #define CONFIG_JFFS2_CMDLINE |
| 218 | #define MTDIDS_DEFAULT "nor0=bab7xx-0" |
| 219 | #define MTDPARTS_DEFAULT "mtdparts=bab7xx-0:-(jffs2)" |
| 220 | */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 221 | |
| 222 | #define CFG_MONITOR_BASE CFG_FLASH_BASE |
| 223 | #define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ |
| 224 | #define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ |
| 225 | #undef CFG_MEMTEST |
| 226 | |
| 227 | /* |
| 228 | * Environment settings |
| 229 | */ |
| 230 | #define CONFIG_ENV_OVERWRITE |
| 231 | #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
| 232 | #define CFG_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */ |
| 233 | #define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ |
| 234 | /* |
| 235 | * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus, |
| 236 | * user applications can use the remaining space for other purposes. |
| 237 | */ |
| 238 | #define CFG_ENV_ADDR (CFG_NVRAM_SIZE +0x10 -0x800) |
| 239 | #define CFG_NV_SROM_COPY_ADDR (CFG_NVRAM_SIZE +0x10 -0x400) |
| 240 | #define CFG_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */ |
| 241 | #define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ |
| 242 | |
| 243 | /* |
| 244 | * Serial devices |
| 245 | */ |
| 246 | #define CFG_NS16550 |
| 247 | #define CFG_NS16550_SERIAL |
| 248 | #define CFG_NS16550_REG_SIZE 1 |
| 249 | #define CFG_NS16550_CLK 1843200 |
| 250 | #define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) |
| 251 | #define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) |
| 252 | |
| 253 | /* |
| 254 | * PCI stuff |
| 255 | */ |
| 256 | #define CONFIG_PCI /* include pci support */ |
| 257 | #define CONFIG_PCI_PNP /* pci plug-and-play */ |
| 258 | #define CONFIG_PCI_HOST PCI_HOST_AUTO |
| 259 | #undef CONFIG_PCI_SCAN_SHOW |
| 260 | |
| 261 | /* |
| 262 | * Video console (graphic: SMI LynxEM, keyboard: i8042) |
| 263 | */ |
| 264 | #define CONFIG_VIDEO |
| 265 | #define CONFIG_CFB_CONSOLE |
| 266 | #define CONFIG_VIDEO_SMI_LYNXEM |
| 267 | #define CONFIG_I8042_KBD |
| 268 | #define CONFIG_VIDEO_LOGO |
| 269 | #define CONFIG_CONSOLE_TIME |
| 270 | #define CONFIG_CONSOLE_EXTRA_INFO |
| 271 | #define CONFIG_CONSOLE_CURSOR |
| 272 | #define CFG_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */ |
| 273 | |
| 274 | /* |
| 275 | * IDE/SCSI globals |
| 276 | */ |
| 277 | #ifndef __ASSEMBLY__ |
| 278 | extern unsigned int eltec_board; |
| 279 | extern unsigned int ata_reset_time; |
| 280 | extern unsigned int scsi_reset_time; |
| 281 | extern unsigned short scsi_dev_id; |
| 282 | extern unsigned int scsi_max_scsi_id; |
| 283 | extern unsigned char scsi_sym53c8xx_ccf; |
| 284 | #endif |
| 285 | |
| 286 | /* |
| 287 | * ATAPI Support (experimental) |
| 288 | */ |
| 289 | #define CONFIG_ATAPI |
| 290 | #define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ |
| 291 | #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ |
| 292 | |
| 293 | #define CFG_ATA_BASE_ADDR CFG_60X_PCI_IO_OFFSET /* base address */ |
| 294 | #define CFG_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */ |
| 295 | #define CFG_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */ |
| 296 | #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ |
| 297 | #define CFG_ATA_REG_OFFSET 0 /* reg offset */ |
| 298 | #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ |
| 299 | |
| 300 | #define ATA_RESET_TIME (ata_reset_time) |
| 301 | |
| 302 | #undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ |
| 303 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
| 304 | |
| 305 | /* |
| 306 | * SCSI support (experimental) only SYM53C8xx supported |
| 307 | */ |
| 308 | #define CONFIG_SCSI_SYM53C8XX |
| 309 | #define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */ |
| 310 | #define CFG_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */ |
| 311 | #define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ |
| 312 | #define CFG_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */ |
| 313 | #define CFG_SCSI_MAX_DEVICE (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */ |
| 314 | #define CFG_SCSI_SPIN_UP_TIME (scsi_reset_time) |
| 315 | |
| 316 | /* |
| 317 | * Partion suppport |
| 318 | */ |
| 319 | #define CONFIG_DOS_PARTITION |
| 320 | #define CONFIG_MAC_PARTITION |
| 321 | #define CONFIG_ISO_PARTITION |
| 322 | |
| 323 | /* |
| 324 | * Winbond Configuration |
| 325 | */ |
| 326 | #define CFG_WINBOND_83C553 1 /* has a winbond bridge */ |
| 327 | #define CFG_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */ |
| 328 | #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */ |
| 329 | #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */ |
| 330 | |
| 331 | /* |
| 332 | * NS87308 Configuration |
| 333 | */ |
| 334 | #define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */ |
| 335 | #define CFG_NS87308_BADDR_10 1 |
| 336 | #define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 337 | CFG_NS87308_UART2 | \ |
| 338 | CFG_NS87308_KBC1 | \ |
| 339 | CFG_NS87308_MOUSE | \ |
| 340 | CFG_NS87308_FDC | \ |
| 341 | CFG_NS87308_RARP | \ |
| 342 | CFG_NS87308_GPIO | \ |
| 343 | CFG_NS87308_POWRMAN | \ |
| 344 | CFG_NS87308_RTC_APC ) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 345 | |
| 346 | #define CFG_NS87308_PS2MOD |
| 347 | #define CFG_NS87308_GPIO_BASE 0x0220 |
| 348 | #define CFG_NS87308_PWMAN_BASE 0x0460 |
| 349 | #define CFG_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */ |
| 350 | |
| 351 | /* |
| 352 | * set up the NVRAM access registers |
| 353 | * NVRAM's controlled by the configurable CS line from the 87308 |
| 354 | */ |
| 355 | #define CFG_NS87308_CS0_BASE 0x0076 |
| 356 | #define CFG_NS87308_CS0_CONF 0x40 |
| 357 | #define CFG_NS87308_CS1_BASE 0x0070 |
| 358 | #define CFG_NS87308_CS1_CONF 0x1C |
| 359 | #define CFG_NS87308_CS2_BASE 0x0071 |
| 360 | #define CFG_NS87308_CS2_CONF 0x1C |
| 361 | |
| 362 | #define CONFIG_RTC_MK48T59 |
| 363 | |
| 364 | /* |
| 365 | * Initial BATs |
| 366 | */ |
| 367 | #if 1 |
| 368 | |
| 369 | #define CFG_IBAT0L 0 |
| 370 | #define CFG_IBAT0U 0 |
| 371 | #define CFG_DBAT0L CFG_IBAT1L |
| 372 | #define CFG_DBAT0U CFG_IBAT1U |
| 373 | |
| 374 | #define CFG_IBAT1L 0 |
| 375 | #define CFG_IBAT1U 0 |
| 376 | #define CFG_DBAT1L CFG_IBAT1L |
| 377 | #define CFG_DBAT1U CFG_IBAT1U |
| 378 | |
| 379 | #define CFG_IBAT2L 0 |
| 380 | #define CFG_IBAT2U 0 |
| 381 | #define CFG_DBAT2L CFG_IBAT2L |
| 382 | #define CFG_DBAT2U CFG_IBAT2U |
| 383 | |
| 384 | #define CFG_IBAT3L 0 |
| 385 | #define CFG_IBAT3U 0 |
| 386 | #define CFG_DBAT3L CFG_IBAT3L |
| 387 | #define CFG_DBAT3U CFG_IBAT3U |
| 388 | |
| 389 | #else |
| 390 | |
| 391 | /* SDRAM */ |
| 392 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW) |
| 393 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 394 | #define CFG_DBAT0L CFG_IBAT1L |
| 395 | #define CFG_DBAT0U CFG_IBAT1U |
| 396 | |
| 397 | /* address range for flashes */ |
| 398 | #define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) |
| 399 | #define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) |
| 400 | #define CFG_DBAT1L CFG_IBAT1L |
| 401 | #define CFG_DBAT1U CFG_IBAT1U |
| 402 | |
| 403 | /* ISA IO space */ |
| 404 | #define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) |
| 405 | #define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) |
| 406 | #define CFG_DBAT2L CFG_IBAT2L |
| 407 | #define CFG_DBAT2U CFG_IBAT2U |
| 408 | |
| 409 | /* ISA memory space */ |
| 410 | #define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) |
| 411 | #define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) |
| 412 | #define CFG_DBAT3L CFG_IBAT3L |
| 413 | #define CFG_DBAT3U CFG_IBAT3U |
| 414 | |
| 415 | #endif |
| 416 | |
| 417 | /* |
| 418 | * Speed settings are board specific |
| 419 | */ |
| 420 | #ifndef __ASSEMBLY__ |
| 421 | extern unsigned long bab7xx_get_bus_freq (void); |
| 422 | extern unsigned long bab7xx_get_gclk_freq (void); |
| 423 | #endif |
| 424 | #define CFG_BUS_HZ bab7xx_get_bus_freq() |
| 425 | #define CFG_BUS_CLK CFG_BUS_HZ |
| 426 | #define CFG_CPU_CLK bab7xx_get_gclk_freq() |
| 427 | |
| 428 | /* |
| 429 | * For booting Linux, the board info and command line data |
| 430 | * have to be in the first 8 MB of memory, since this is |
| 431 | * the maximum mapped by the Linux kernel during initialization. |
| 432 | */ |
| 433 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 434 | |
| 435 | /* |
| 436 | * Cache Configuration |
| 437 | */ |
| 438 | #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
| 439 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 440 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 441 | #endif |
| 442 | |
| 443 | /* |
| 444 | * L2 Cache Configuration is board specific for BAB740/BAB750 |
| 445 | * Init values read from revision srom. |
| 446 | */ |
| 447 | #undef CFG_L2 |
| 448 | #define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 449 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 450 | #define L2_ENABLE (L2_INIT | L2CR_L2E) |
| 451 | |
| 452 | #define CFG_L2_BAB7xx |
| 453 | |
| 454 | /* |
| 455 | * Internal Definitions |
| 456 | * |
| 457 | * Boot Flags |
| 458 | */ |
| 459 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 460 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 461 | |
| 462 | |
| 463 | #define CONFIG_NET_MULTI /* Multi ethernet cards support */ |
| 464 | #define CONFIG_TULIP |
| 465 | #define CONFIG_TULIP_SELECT_MEDIA |
| 466 | |
| 467 | #endif /* __CONFIG_H */ |