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wdenk57b2d802003-06-27 21:31:46 +00001 PowerPC 440
wdenkc6097192002-11-03 00:24:07 +00002
wdenk57b2d802003-06-27 21:31:46 +00003 Last Update: September 11, 2002
wdenkc6097192002-11-03 00:24:07 +00004=======================================================================
5
6
7OVERVIEW
8============
9
10Support for the ppc440 is contained in the cpu/ppc44x directory
11and enabled via the CONFIG_440 flag. It is largely based on the
12405gp code. A sample board support implementation is contained
13in the board/ebony directory.
14
15All testing was performed using the IBM Ebony board using both
16Rev B and Rev C silicon. However, since the Rev B. silicon has
17extensive errata, support for Rev B. is minimal (it boots, and
18features such as i2c, pci, tftpboot, etc. seem to work ok).
19The expectation is that all new board designs will be using
20Rev C or later parts -- if not, you may be in for a rough ride ;-)
21
22The ppc440 port does a fair job of keeping "board-specific" code
23out of the "cpu-specific" source. The goal of course was to
24provide mechanisms for each board to customize without having
25to clutter the cpu-specific source with a lot of ifdefs. Most
26of these mechanisms are described in the following sections.
27
28
29MEMORY MANAGEMENT
30=================
31
32The ppc440 doesn't run in "real mode". The MMU must be active
33at all times. Additionally, the 440 implements a 36-bit physical
34memory space that gets mapped into the PowerPC 32-bit virtual
35address space. So things like memory-mapped peripherals, etc must
36all be mapped in. Once this is done, the 32-bit virtual address
37space is then viewed as though it were physical memory.
38
39However, this means that memory, peripherals, etc can be configured
40to appear (mostly) anywhere in the virtual address space. Each board
41must define its own mappings using the tlbtab (see board/ebony/init.S).
42The actual TLB setup is performed by the cpu-specific code.
43
44Although each board is free to define its own mappings, there are
45several definitions to be aware of. These definitions may be used in
46the cpu-specific code (vs. board-specific code), so you should
47at least review these before deciding to make any changes ... it
48will probably save you some headaches ;-)
49
50CFG_SDRAM_BASE - The virtual address where SDRAM is mapped (always 0)
51
52CFG_FLASH_BASE - The virtual address where FLASH is mapped.
53
54CFG_PCI_MEMBASE - The virtual address where PCI-bus memory is mapped.
55 This mapping provides access to PCI-bus memory.
56
57CFG_PERIPHERAL_BASE - The virtual address where the 440 memory-mapped
58 peripherals are mapped. (e.g. -- UART registers, IIC registers, etc).
59
60CFG_ISRAM_BASE - The virtual address where the 440 internal SRAM is
61 mapped. The internal SRAM is equivalent to 405gp OCM and is used
62 for the initial stack.
63
64CFG_PCI_BASE - The virtual address where the 440 PCI-x bridge config
65 registers are mapped.
66
67CFG_PCI_TARGBASE - The PCI address that is mapped to the virtual address
68 defined by CFG_PCI_MEMBASE.
69
70
71UART / SERIAL
72=================
73
74The UART port works fine when an external serial clock is provided
75(like the one on the Ebony board) and when using internal clocking.
76This is controlled with the CFG_EXT_SERIAL_CLOCK flag. When using
77internal clocking, the "ideal baud rate" settings in the 440GP
78user manual are automatically calculated.
79
80CONFIG_SERIAL_SOFTWARE_FIFO enables interrupt-driven serial operation.
81But the last time I checked, interrupts were initialized after the
82serial port causing the interrupt handler to be removed from the
83handler table. This will probably be fixed soon ... or fix it
84yourself and submit a patch :-)
85
86
87I2C
88=================
89
90The i2c utilities have been tested on both Rev B. and Rev C. and
91look good. The iprobe command implementation has been updated to
92allow for 'skipped' addresses. Some i2c slaves are write only and
93cause problems when a probe (read) is performed (for example the
94CDCV850 clock controller at address 0x69 on the ebony board).
95
96To prevent probing certain addresses you can define the
97CFG_I2C_NOPROBES macro in your board-specific header file. When
98defined, all specified addresses are skipped during a probe.
99The addresses that are skipped will be displayed in the output
100of the iprobe command.
101
102For example, to prevent probing address 0x69, define the macro as
103follows:
104
105#define CFG_I2C_NOPROBES {0x69}
106
107Similarly, to prevent probing addresses 0x69 and 0x70, define the
108macro a:
109
110#define CFG_I2C_NOPROBES {0x69, 0x70}
111
112
113DDR SDRAM CONTROLLER
114====================
115
116SDRAM controller intialization using Serial Presence Detect (SPD) is
117now supported (thanks Jun). It is enabled by defining CONFIG_SPD_EEPROM.
118The i2c eeprom addresses are controlled by the SPD_EEPROM_ADDRESS macro.
119
120NOTE: The SPD_EEPROM_ADDRESS macro is defined differently than for other
121processors. Traditionally, it defined a single address. For the 440 it
122defines an array of addresses to support multiple banks. Address order
123is significant: the addresses are used in order to program the BankN
124registers. For example, two banks with i2c addresses of 0x53 (bank 0)
125and 0x52 (bank 1) would be defined as follows:
126
127#define SPD_EEPROM_ADDRESS {0x53,0x52}
128
129
130PCI-X BRIDGE
131====================
132
133PCI is an area that requires lots of flexibility since every board has
134its own set of constraints and configuration. This section describes the
135440 implementation.
136
137CPC0_STRP1[PISE] -- if the PISE strap bit is not asserted, PCI init
138is aborted and an indication is printed. This is NOT considered an
139error -- only an indication that PCI shouldn't be initialized. This
140gives you a chance to edit the i2c bootstrap eeproms using the i2c
141utilities once you get to the U-Boot command prompt. NOTE: the default
142440 bootstrap options (not using i2c eeprom) negates this bit.
143
144The cpu-specific code sets up a default pci_controller structure
145that maps in a single PCI I/O space and PCI memory space. The I/O
146space begins at PCI I/O address 0 and the PCI memory space is
147256 MB starting at PCI address CFG_PCI_TARGBASE. After the
148pci_controller structure is initialized, the cpu-specific code will
149call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is
150defined. This routine is implemented by board-specific code & is where
151the board can over-ride/extend the default pci_controller structure
152settings and do other pre-initialization tasks. If pci_pre_init()
153returns a value of zero, PCI initialization is aborted; otherwise the
154controller structure is registered and initialization continues.
155
156The default 440GP PCI target configuration is minimal -- it assumes that
157the strapping registers are set as necessary. Since the strapping bits
158provide very limited flexibility, you may want to customize the boards
159target configuration. If CFG_PCI_TARGET_INIT is defined, the cpu-specific
160code will call the routine pci_target_init() which you must implement
161in your board-specific code.
162
163Target initialization is completed by the cpu-specific code by
164initializing the subsystem id and subsystem vendor id, and then ensuring
165that the 'enable host configuration' bit in the PCIX0_BRDGOPT2 is set.
166
167The default PCI master initialization maps in 256 MB of pci memory
168starting at PCI address CFG_PCI_MEMBASE. To customize this, define
169PCI_MASTER_INIT. This will call the routine pci_master_init() in your
170board-specific code rather than performing the default master
171initialization.
172
173The decision to perform PCI host configuration must often be determined
174at run time. The ppc440 port differs from most other implementations in
175that it requires the board to determine its host configuration at run
176time rather than by using compile-time flags. This shouldn't create a
177large impact on the board-specific code since the board only needs to
178implement a single routine that returns a zero or non-zero value:
179is_pci_host().
180
181Justification for this becomes clear when considering systems running
182in a cPCI environment:
183
1841. Arbiter strapping: Many cPCI boards provide an external arbiter (often
185part of the PCI-to-PCI bridge). Even though the arbiter is external (the
186arbiter strapping is negated), the CPU may still be required to perform
187local PCI bus configuration.
188
1892. Host only: PPMC boards must sample the MONARCH# signal at run-time.
190Depending on the configuration of the carrier boar, the PPMC board must
191determine if it should configure the PCI bus at run-time. And in most
192cases, access to the MONARCH# signal is board-specific (e.g. via
193board-specific FPGA registers, etc).
194
195In any event, the is_pci_host() routine gives each board the opportunity
196to decide at run-time. If your board is always configured a certain way,
197then just hardcode a return of 1 or 0 as appropriate.
198
199
wdenkc6097192002-11-03 00:24:07 +0000200Regards,
201--Scott
202<smcnutt@artesyncp.com>